[PATCH 0/4] cpufreq: Use cpufreq-cpu0 driver for Exynos3250

[PATCH 0/4] cpufreq: Use cpufreq-cpu0 driver for Exynos3250

[Chanwoo Choi]

This patchset use cpufreq-cpu0 driver to support Exynos3250 cpufreq. So, this
patchset is based on following patchset[1] by Thomas Abraham.
 [1] http://www.spinics.net/lists/linux-samsung-soc/msg31593.html

Chanwoo Choi (4):
  clk: samsung: exynos3250: Use cpu-clock provider type to support cpufreq
  clk: samsung: Add support for cpu clocks of Exynos3250
  Documentation: devicetree: Add cpu clock configuration data binding for Exynos3250
  ARM: dts: Exynos: Add cpu clock table and armclk divider table for Exynos3250

 .../devicetree/bindings/clock/exynos3250-clock.txt | 32 ++++++++++++++++++++++
 arch/arm/boot/dts/exynos3250.dtsi                  | 28 +++++++++++++++++++
 drivers/clk/samsung/clk-cpu.c                      | 31 +++++++++++++++++----
 drivers/clk/samsung/clk-exynos3250.c               | 14 +++++++---
 4 files changed, 96 insertions(+), 9 deletions(-)

-- 
1.8.0

[PATCH 0/4] cpufreq: Use cpufreq-cpu0 driver for Exynos3250

[Chanwoo Choi]

This patchset use cpufreq-cpu0 driver to support Exynos3250 cpufreq. So, this
patchset is based on following patchset[1] by Thomas Abraham.
 [1] http://www.spinics.net/lists/linux-samsung-soc/msg31593.html

Chanwoo Choi (4):
  clk: samsung: exynos3250: Use cpu-clock provider type to support cpufreq
  clk: samsung: Add support for cpu clocks of Exynos3250
  Documentation: devicetree: Add cpu clock configuration data binding for Exynos3250
  ARM: dts: Exynos: Add cpu clock table and armclk divider table for Exynos3250

 .../devicetree/bindings/clock/exynos3250-clock.txt | 32 ++++++++++++++++++++++
 arch/arm/boot/dts/exynos3250.dtsi                  | 28 +++++++++++++++++++
 drivers/clk/samsung/clk-cpu.c                      | 31 +++++++++++++++++----
 drivers/clk/samsung/clk-exynos3250.c               | 14 +++++++---
 4 files changed, 96 insertions(+), 9 deletions(-)

-- 
1.8.0

[PATCH 1/4] clk: samsung: exynos3250: Use cpu-clock provider type to support cpufreq

[Chanwoo Choi]

This patch use cpu-clock provider type to support cpufreq for Exynos3250. The
clock-exynos3250.c didn't add separate 'arm_clk' divider for 'div_core2'.
The 'div_core2' can be represented as a cpu-clock type and then use 'div_core2'
directly to change cpu clock.

Cc: Tomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-exynos3250.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index 7a17bd4..9905fd4 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -351,8 +351,10 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
 	MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
 	    SRC_CPU, 24, 1),
 	MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
-	MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1),
-	MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+	MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1, 0,
+			CLK_MUX_READ_ONLY),
+	MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+			CLK_SET_RATE_PARENT, 0),
 };
 
 static struct samsung_div_clock div_clks[] __initdata = {
@@ -441,11 +443,13 @@ static struct samsung_div_clock div_clks[] __initdata = {
 
 	/* DIV_CPU0 */
 	DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
-	DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
+	DIV_F(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
 	DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
 	DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
 	DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),
-	DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),
+	DIV_F(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
 
 	/* DIV_CPU1 */
 	DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
@@ -774,6 +778,8 @@ static void __init exynos3250_cmu_init(struct device_node *np)
 	samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks));
 	samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
 	samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
+	exynos_register_arm_clock(ctx, CLK_DIV_CORE2, mout_core_p[0],
+				mout_core_p[1], np);
 
 	exynos3250_clk_sleep_init();
 }
-- 
1.8.0

[PATCH 1/4] clk: samsung: exynos3250: Use cpu-clock provider type to support cpufreq

[Chanwoo Choi]

This patch use cpu-clock provider type to support cpufreq for Exynos3250. The
clock-exynos3250.c didn't add separate 'arm_clk' divider for 'div_core2'.
The 'div_core2' can be represented as a cpu-clock type and then use 'div_core2'
directly to change cpu clock.

Cc: Tomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-exynos3250.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index 7a17bd4..9905fd4 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -351,8 +351,10 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
 	MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p,
 	    SRC_CPU, 24, 1),
 	MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1),
-	MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1),
-	MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+	MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1, 0,
+			CLK_MUX_READ_ONLY),
+	MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+			CLK_SET_RATE_PARENT, 0),
 };
 
 static struct samsung_div_clock div_clks[] __initdata = {
@@ -441,11 +443,13 @@ static struct samsung_div_clock div_clks[] __initdata = {
 
 	/* DIV_CPU0 */
 	DIV(CLK_DIV_CORE2, "div_core2", "div_core", DIV_CPU0, 28, 3),
-	DIV(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
+	DIV_F(CLK_DIV_APLL, "div_apll", "mout_apll", DIV_CPU0, 24, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
 	DIV(CLK_DIV_PCLK_DBG, "div_pclk_dbg", "div_core2", DIV_CPU0, 20, 3),
 	DIV(CLK_DIV_ATB, "div_atb", "div_core2", DIV_CPU0, 16, 3),
 	DIV(CLK_DIV_COREM, "div_corem", "div_core2", DIV_CPU0, 4, 3),
-	DIV(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3),
+	DIV_F(CLK_DIV_CORE, "div_core", "mout_core", DIV_CPU0, 0, 3,
+			CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
 
 	/* DIV_CPU1 */
 	DIV(CLK_DIV_HPM, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
@@ -774,6 +778,8 @@ static void __init exynos3250_cmu_init(struct device_node *np)
 	samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks));
 	samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
 	samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));
+	exynos_register_arm_clock(ctx, CLK_DIV_CORE2, mout_core_p[0],
+				mout_core_p[1], np);
 
 	exynos3250_clk_sleep_init();
 }
-- 
1.8.0

[PATCH 2/4] clk: samsung: Add support for cpu clocks of Exynos3250

[Chanwoo Choi]

This patch add support for a new clock type for Exynos3250 CPU clock provider
and modify little difference of DIV_CPU0 between Exynos4 and Exynos3250.

Cc: Tomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-cpu.c | 31 ++++++++++++++++++++++++++-----
 1 file changed, 26 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 13fa4c5..ccdcd6a 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -36,6 +36,9 @@
 #define EXYNOS4210_DIV1_HPM_MASK	((0x7 << 0) | (0x7 << 4))
 #define EXYNOS4210_MUX_HPM_MASK		(1 << 20)
 
+#define EXYNOS3250_DIV_CPU0(d3, d2, d1, d0)			\
+		(((d3) << 24) | ((d2) << 20) | ((d1) << 16) | ((d0) <<  4))
+
 /**
  * struct exynos4210_armclk_data: config data to setup exynos4210 cpu clocks.
  * @prate:	frequency of the parent clock.
@@ -384,11 +387,27 @@ static int __init exynos4210_armclk_parser(struct device_node *np, void **data)
 			ptr = of_prop_next_u32(prop, ptr, &cfg[col]);
 
 		tdata->prate = cfg[0] * 1000;
-		tdata->div0 = EXYNOS4210_DIV_CPU0(cfg[6], cfg[5], cfg[4],
-						cfg[3], cfg[2], cfg[1]);
-		tdata->div1 = cells == 10 ?
-				EXYNOS4210_DIV_CPU1(cfg[9], cfg[8], cfg[7]) :
-				EXYNOS4210_DIV_CPU1(0, cfg[8], cfg[7]);
+
+		switch (cells) {
+		case 7:
+			tdata->div0 = EXYNOS3250_DIV_CPU0(cfg[4], cfg[3],
+						cfg[2], cfg[1]);
+			tdata->div1 = EXYNOS4210_DIV_CPU1(0, cfg[6], cfg[5]);
+			break;
+		case 9:
+			tdata->div0 = EXYNOS4210_DIV_CPU0(cfg[6], cfg[5],
+						cfg[4], cfg[3], cfg[2], cfg[1]);
+			tdata->div1 = EXYNOS4210_DIV_CPU1(0, cfg[8], cfg[7]);
+			break;
+		case 10:
+			tdata->div0 = EXYNOS4210_DIV_CPU0(cfg[6], cfg[5],
+						cfg[4], cfg[3], cfg[2], cfg[1]);
+			tdata->div1 = EXYNOS4210_DIV_CPU1(cfg[9], cfg[8],
+						cfg[7]);
+			break;
+		default:
+			return -EINVAL;
+		}
 	}
 	tdata->prate = 0;
 	return 0;
@@ -409,6 +428,8 @@ static const struct exynos_cpuclk_soc_data exynos5250_cpuclk_soc_data = {
 };
 
 static const struct of_device_id exynos_clock_ids_armclk[] = {
+	{ .compatible = "samsung,exynos3250-cmu",
+			.data = &exynos4210_cpuclk_soc_data, },
 	{ .compatible = "samsung,exynos4210-clock",
 			.data = &exynos4210_cpuclk_soc_data, },
 	{ .compatible = "samsung,exynos4412-clock",
-- 
1.8.0

[PATCH 2/4] clk: samsung: Add support for cpu clocks of Exynos3250

[Chanwoo Choi]

This patch add support for a new clock type for Exynos3250 CPU clock provider
and modify little difference of DIV_CPU0 between Exynos4 and Exynos3250.

Cc: Tomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-cpu.c | 31 ++++++++++++++++++++++++++-----
 1 file changed, 26 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 13fa4c5..ccdcd6a 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -36,6 +36,9 @@
 #define EXYNOS4210_DIV1_HPM_MASK	((0x7 << 0) | (0x7 << 4))
 #define EXYNOS4210_MUX_HPM_MASK		(1 << 20)
 
+#define EXYNOS3250_DIV_CPU0(d3, d2, d1, d0)			\
+		(((d3) << 24) | ((d2) << 20) | ((d1) << 16) | ((d0) <<  4))
+
 /**
  * struct exynos4210_armclk_data: config data to setup exynos4210 cpu clocks.
  * @prate:	frequency of the parent clock.
@@ -384,11 +387,27 @@ static int __init exynos4210_armclk_parser(struct device_node *np, void **data)
 			ptr = of_prop_next_u32(prop, ptr, &cfg[col]);
 
 		tdata->prate = cfg[0] * 1000;
-		tdata->div0 = EXYNOS4210_DIV_CPU0(cfg[6], cfg[5], cfg[4],
-						cfg[3], cfg[2], cfg[1]);
-		tdata->div1 = cells == 10 ?
-				EXYNOS4210_DIV_CPU1(cfg[9], cfg[8], cfg[7]) :
-				EXYNOS4210_DIV_CPU1(0, cfg[8], cfg[7]);
+
+		switch (cells) {
+		case 7:
+			tdata->div0 = EXYNOS3250_DIV_CPU0(cfg[4], cfg[3],
+						cfg[2], cfg[1]);
+			tdata->div1 = EXYNOS4210_DIV_CPU1(0, cfg[6], cfg[5]);
+			break;
+		case 9:
+			tdata->div0 = EXYNOS4210_DIV_CPU0(cfg[6], cfg[5],
+						cfg[4], cfg[3], cfg[2], cfg[1]);
+			tdata->div1 = EXYNOS4210_DIV_CPU1(0, cfg[8], cfg[7]);
+			break;
+		case 10:
+			tdata->div0 = EXYNOS4210_DIV_CPU0(cfg[6], cfg[5],
+						cfg[4], cfg[3], cfg[2], cfg[1]);
+			tdata->div1 = EXYNOS4210_DIV_CPU1(cfg[9], cfg[8],
+						cfg[7]);
+			break;
+		default:
+			return -EINVAL;
+		}
 	}
 	tdata->prate = 0;
 	return 0;
@@ -409,6 +428,8 @@ static const struct exynos_cpuclk_soc_data exynos5250_cpuclk_soc_data = {
 };
 
 static const struct of_device_id exynos_clock_ids_armclk[] = {
+	{ .compatible = "samsung,exynos3250-cmu",
+			.data = &exynos4210_cpuclk_soc_data, },
 	{ .compatible = "samsung,exynos4210-clock",
 			.data = &exynos4210_cpuclk_soc_data, },
 	{ .compatible = "samsung,exynos4412-clock",
-- 
1.8.0

[PATCH 3/4] Documentation: devicetree: Add cpu clock configuration data binding for Exynos3250

[Chanwoo Choi]

The clock block of Exynos3250 add new properties to support cpu clock provider.
To register cpu clock provider of Exynos3250, must need armclk-provider-table
which includes various dividers to change CPU clock to support Exynos3250 cpufreq.

Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 .../devicetree/bindings/clock/exynos3250-clock.txt | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
index aadc9c5..189b506 100644
--- a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
@@ -13,6 +13,25 @@ Required Properties:
 
 - #clock-cells: should be 1.
 
+- samsung,armclk-divider-table: when the frequency of the APLL is changed
+  the divider clocks in CMU_CPU clock domain also need to be updated. These
+  divider clocks have SoC specific divider clock output requirements for a
+  specific APLL clock speeds. When APLL clock rate is changed, these divider
+  clocks are reprogrammed with pre-determined values in order to maintain the
+  SoC specific divider clock outputs. This property lists the divider values
+  for divider clocks in the CMU_CPU block for supported APLL clock speeds.
+  The format of each entry included in the arm-frequency-table should be
+  as defined below
+
+      cell #1: expected arm clock parent frequency
+      cell #2 ~ cell #7: value of clock divider in the following order
+		corem_ratio, atb_ratio, pclk_dbg_ratio, apll_ratio,
+		copy_ratio, hpm_ratio
+
+- samsung,armclk-cells: defines the number of cells in
+  samsung,armclk-divider-table property. The value of this property depends on
+  the SoC type.
+
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume.
 
@@ -26,6 +45,19 @@ Example 1: An example of a clock controller node is listed below.
 		compatible = "samsung,exynos3250-cmu";
 		reg = <0x10030000 0x20000>;
 		#clock-cells = <1>;
+
+		samsung,armclk-cells = <7>;
+		samsung,armclk-divider-table =
+			<1000000 1 4 7 1 7 7>,
+			<900000  1 3 7 1 7 7>,
+			<800000  1 3 7 1 7 7>,
+			<700000  1 3 7 1 7 7>,
+			<600000  1 3 7 1 7 7>,
+			<500000  1 3 7 1 7 7>,
+			<400000  1 3 7 1 7 7>,
+			<300000  1 3 5 1 7 7>,
+			<200000  1 3 3 1 7 7>,
+			<100000  1 1 1 1 7 7>;
 	};
 
 Example 2: UART controller node that consumes the clock generated by the clock
-- 
1.8.0

[PATCH 3/4] Documentation: devicetree: Add cpu clock configuration data binding for Exynos3250

[Chanwoo Choi]

The clock block of Exynos3250 add new properties to support cpu clock provider.
To register cpu clock provider of Exynos3250, must need armclk-provider-table
which includes various dividers to change CPU clock to support Exynos3250 cpufreq.

Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 .../devicetree/bindings/clock/exynos3250-clock.txt | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
index aadc9c5..189b506 100644
--- a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
@@ -13,6 +13,25 @@ Required Properties:
 
 - #clock-cells: should be 1.
 
+- samsung,armclk-divider-table: when the frequency of the APLL is changed
+  the divider clocks in CMU_CPU clock domain also need to be updated. These
+  divider clocks have SoC specific divider clock output requirements for a
+  specific APLL clock speeds. When APLL clock rate is changed, these divider
+  clocks are reprogrammed with pre-determined values in order to maintain the
+  SoC specific divider clock outputs. This property lists the divider values
+  for divider clocks in the CMU_CPU block for supported APLL clock speeds.
+  The format of each entry included in the arm-frequency-table should be
+  as defined below
+
+      cell #1: expected arm clock parent frequency
+      cell #2 ~ cell #7: value of clock divider in the following order
+		corem_ratio, atb_ratio, pclk_dbg_ratio, apll_ratio,
+		copy_ratio, hpm_ratio
+
+- samsung,armclk-cells: defines the number of cells in
+  samsung,armclk-divider-table property. The value of this property depends on
+  the SoC type.
+
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume.
 
@@ -26,6 +45,19 @@ Example 1: An example of a clock controller node is listed below.
 		compatible = "samsung,exynos3250-cmu";
 		reg = <0x10030000 0x20000>;
 		#clock-cells = <1>;
+
+		samsung,armclk-cells = <7>;
+		samsung,armclk-divider-table =
+			<1000000 1 4 7 1 7 7>,
+			<900000  1 3 7 1 7 7>,
+			<800000  1 3 7 1 7 7>,
+			<700000  1 3 7 1 7 7>,
+			<600000  1 3 7 1 7 7>,
+			<500000  1 3 7 1 7 7>,
+			<400000  1 3 7 1 7 7>,
+			<300000  1 3 5 1 7 7>,
+			<200000  1 3 3 1 7 7>,
+			<100000  1 1 1 1 7 7>;
 	};
 
 Example 2: UART controller node that consumes the clock generated by the clock
-- 
1.8.0

[PATCH 4/4] ARM: dts: Exynos: Add cpu clock table and armclk divider table for Exynos3250

[Chanwoo Choi]

This patch add cpu clock table and armclk divier table to support
generic cpufreq-cpu0 driver for Exynos3250.

Cc: Tomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/boot/dts/exynos3250.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 3e678fa..df0efd0 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -50,6 +50,21 @@
 			compatible = "arm,cortex-a7";
 			reg = <0>;
 			clock-frequency = <1000000000>;
+			clocks = <&cmu CLK_DIV_CORE2>;
+			clock-names = "cpu";
+
+			operating-points = <
+				1000000 1150000
+				900000  1112500
+				800000  1075000
+				700000  1037500
+				600000  1000000
+				500000  962500
+				400000  925000
+				300000  887500
+				200000  850000
+				100000  850000
+			>;
 		};
 
 		cpu1: cpu@1 {
@@ -159,6 +174,19 @@
 			compatible = "samsung,exynos3250-cmu";
 			reg = <0x10030000 0x20000>;
 			#clock-cells = <1>;
+
+			samsung,armclk-cells = <7>;
+			samsung,armclk-divider-table =
+				<1000000 1 4 7 1 7 7>,
+				<900000  1 3 7 1 7 7>,
+				<800000  1 3 7 1 7 7>,
+				<700000  1 3 7 1 7 7>,
+				<600000  1 3 7 1 7 7>,
+				<500000  1 3 7 1 7 7>,
+				<400000  1 3 7 1 7 7>,
+				<300000  1 3 5 1 7 7>,
+				<200000  1 3 3 1 7 7>,
+				<100000  1 1 1 1 7 7>;
 		};
 
 		rtc: rtc@10070000 {
-- 
1.8.0

[PATCH 4/4] ARM: dts: Exynos: Add cpu clock table and armclk divider table for Exynos3250

[Chanwoo Choi]

This patch add cpu clock table and armclk divier table to support
generic cpufreq-cpu0 driver for Exynos3250.

Cc: Tomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 arch/arm/boot/dts/exynos3250.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 3e678fa..df0efd0 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -50,6 +50,21 @@
 			compatible = "arm,cortex-a7";
 			reg = <0>;
 			clock-frequency = <1000000000>;
+			clocks = <&cmu CLK_DIV_CORE2>;
+			clock-names = "cpu";
+
+			operating-points = <
+				1000000 1150000
+				900000  1112500
+				800000  1075000
+				700000  1037500
+				600000  1000000
+				500000  962500
+				400000  925000
+				300000  887500
+				200000  850000
+				100000  850000
+			>;
 		};
 
 		cpu1: cpu at 1 {
@@ -159,6 +174,19 @@
 			compatible = "samsung,exynos3250-cmu";
 			reg = <0x10030000 0x20000>;
 			#clock-cells = <1>;
+
+			samsung,armclk-cells = <7>;
+			samsung,armclk-divider-table =
+				<1000000 1 4 7 1 7 7>,
+				<900000  1 3 7 1 7 7>,
+				<800000  1 3 7 1 7 7>,
+				<700000  1 3 7 1 7 7>,
+				<600000  1 3 7 1 7 7>,
+				<500000  1 3 7 1 7 7>,
+				<400000  1 3 7 1 7 7>,
+				<300000  1 3 5 1 7 7>,
+				<200000  1 3 3 1 7 7>,
+				<100000  1 1 1 1 7 7>;
 		};
 
 		rtc: rtc at 10070000 {
-- 
1.8.0

Re: [PATCH 0/4] cpufreq: Use cpufreq-cpu0 driver for Exynos3250

[Viresh Kumar]

cpufreq@vger.kernel.org is dead now. Anyway you should be using linux-pm
instead.

On 13 June 2014 11:38, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> This patchset use cpufreq-cpu0 driver to support Exynos3250 cpufreq. So, this
> patchset is based on following patchset[1] by Thomas Abraham.
>  [1] http://www.spinics.net/lists/linux-samsung-soc/msg31593.html
>
> Chanwoo Choi (4):
>   clk: samsung: exynos3250: Use cpu-clock provider type to support cpufreq
>   clk: samsung: Add support for cpu clocks of Exynos3250
>   Documentation: devicetree: Add cpu clock configuration data binding for Exynos3250
>   ARM: dts: Exynos: Add cpu clock table and armclk divider table for Exynos3250
>
>  .../devicetree/bindings/clock/exynos3250-clock.txt | 32 ++++++++++++++++++++++
>  arch/arm/boot/dts/exynos3250.dtsi                  | 28 +++++++++++++++++++
>  drivers/clk/samsung/clk-cpu.c                      | 31 +++++++++++++++++----
>  drivers/clk/samsung/clk-exynos3250.c               | 14 +++++++---
>  4 files changed, 96 insertions(+), 9 deletions(-)

Nothing really cpufreq specific. Would *eagerly* wait for the patch that
removes existing driver files :)

[PATCH 0/4] cpufreq: Use cpufreq-cpu0 driver for Exynos3250

[Viresh Kumar]

cpufreq at vger.kernel.org is dead now. Anyway you should be using linux-pm
instead.

On 13 June 2014 11:38, Chanwoo Choi <cw00.choi@samsung.com> wrote:
> This patchset use cpufreq-cpu0 driver to support Exynos3250 cpufreq. So, this
> patchset is based on following patchset[1] by Thomas Abraham.
>  [1] http://www.spinics.net/lists/linux-samsung-soc/msg31593.html
>
> Chanwoo Choi (4):
>   clk: samsung: exynos3250: Use cpu-clock provider type to support cpufreq
>   clk: samsung: Add support for cpu clocks of Exynos3250
>   Documentation: devicetree: Add cpu clock configuration data binding for Exynos3250
>   ARM: dts: Exynos: Add cpu clock table and armclk divider table for Exynos3250
>
>  .../devicetree/bindings/clock/exynos3250-clock.txt | 32 ++++++++++++++++++++++
>  arch/arm/boot/dts/exynos3250.dtsi                  | 28 +++++++++++++++++++
>  drivers/clk/samsung/clk-cpu.c                      | 31 +++++++++++++++++----
>  drivers/clk/samsung/clk-exynos3250.c               | 14 +++++++---
>  4 files changed, 96 insertions(+), 9 deletions(-)

Nothing really cpufreq specific. Would *eagerly* wait for the patch that
removes existing driver files :)

Re: [PATCH 0/4] cpufreq: Use cpufreq-cpu0 driver for Exynos3250

[Thomas Abraham]

On Fri, Jun 13, 2014 at 12:06 PM, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> cpufreq@vger.kernel.org is dead now. Anyway you should be using linux-pm
> instead.
>
> On 13 June 2014 11:38, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> This patchset use cpufreq-cpu0 driver to support Exynos3250 cpufreq. So, this
>> patchset is based on following patchset[1] by Thomas Abraham.
>>  [1] http://www.spinics.net/lists/linux-samsung-soc/msg31593.html
>>
>> Chanwoo Choi (4):
>>   clk: samsung: exynos3250: Use cpu-clock provider type to support cpufreq
>>   clk: samsung: Add support for cpu clocks of Exynos3250
>>   Documentation: devicetree: Add cpu clock configuration data binding for Exynos3250
>>   ARM: dts: Exynos: Add cpu clock table and armclk divider table for Exynos3250
>>
>>  .../devicetree/bindings/clock/exynos3250-clock.txt | 32 ++++++++++++++++++++++
>>  arch/arm/boot/dts/exynos3250.dtsi                  | 28 +++++++++++++++++++
>>  drivers/clk/samsung/clk-cpu.c                      | 31 +++++++++++++++++----
>>  drivers/clk/samsung/clk-exynos3250.c               | 14 +++++++---
>>  4 files changed, 96 insertions(+), 9 deletions(-)
>
> Nothing really cpufreq specific. Would *eagerly* wait for the patch that
> removes existing driver files :)

The next version of the exynos cpufreq cleanup patches are being
prepared. But exynos4x12 cpufreq driver will not be included for
cleanup since the boost frequency bindings need more work.

Thanks,
Thomas.

> --
> To unsubscribe from this list: send the line "unsubscribe cpufreq" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 0/4] cpufreq: Use cpufreq-cpu0 driver for Exynos3250

[Thomas Abraham]

On Fri, Jun 13, 2014 at 12:06 PM, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> cpufreq at vger.kernel.org is dead now. Anyway you should be using linux-pm
> instead.
>
> On 13 June 2014 11:38, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>> This patchset use cpufreq-cpu0 driver to support Exynos3250 cpufreq. So, this
>> patchset is based on following patchset[1] by Thomas Abraham.
>>  [1] http://www.spinics.net/lists/linux-samsung-soc/msg31593.html
>>
>> Chanwoo Choi (4):
>>   clk: samsung: exynos3250: Use cpu-clock provider type to support cpufreq
>>   clk: samsung: Add support for cpu clocks of Exynos3250
>>   Documentation: devicetree: Add cpu clock configuration data binding for Exynos3250
>>   ARM: dts: Exynos: Add cpu clock table and armclk divider table for Exynos3250
>>
>>  .../devicetree/bindings/clock/exynos3250-clock.txt | 32 ++++++++++++++++++++++
>>  arch/arm/boot/dts/exynos3250.dtsi                  | 28 +++++++++++++++++++
>>  drivers/clk/samsung/clk-cpu.c                      | 31 +++++++++++++++++----
>>  drivers/clk/samsung/clk-exynos3250.c               | 14 +++++++---
>>  4 files changed, 96 insertions(+), 9 deletions(-)
>
> Nothing really cpufreq specific. Would *eagerly* wait for the patch that
> removes existing driver files :)

The next version of the exynos cpufreq cleanup patches are being
prepared. But exynos4x12 cpufreq driver will not be included for
cleanup since the boost frequency bindings need more work.

Thanks,
Thomas.

> --
> To unsubscribe from this list: send the line "unsubscribe cpufreq" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 0/4] cpufreq: Use cpufreq-cpu0 driver for Exynos3250

[Chanwoo Choi]

Hi Thomas,

On 06/13/2014 04:00 PM, Thomas Abraham wrote:
> On Fri, Jun 13, 2014 at 12:06 PM, Viresh Kumar <viresh.kumar@linaro.org> wrote:
>> cpufreq@vger.kernel.org is dead now. Anyway you should be using linux-pm
>> instead.
>>
>> On 13 June 2014 11:38, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>> This patchset use cpufreq-cpu0 driver to support Exynos3250 cpufreq. So, this
>>> patchset is based on following patchset[1] by Thomas Abraham.
>>>  [1] http://www.spinics.net/lists/linux-samsung-soc/msg31593.html
>>>
>>> Chanwoo Choi (4):
>>>   clk: samsung: exynos3250: Use cpu-clock provider type to support cpufreq
>>>   clk: samsung: Add support for cpu clocks of Exynos3250
>>>   Documentation: devicetree: Add cpu clock configuration data binding for Exynos3250
>>>   ARM: dts: Exynos: Add cpu clock table and armclk divider table for Exynos3250
>>>
>>>  .../devicetree/bindings/clock/exynos3250-clock.txt | 32 ++++++++++++++++++++++
>>>  arch/arm/boot/dts/exynos3250.dtsi                  | 28 +++++++++++++++++++
>>>  drivers/clk/samsung/clk-cpu.c                      | 31 +++++++++++++++++----
>>>  drivers/clk/samsung/clk-exynos3250.c               | 14 +++++++---
>>>  4 files changed, 96 insertions(+), 9 deletions(-)
>>
>> Nothing really cpufreq specific. Would *eagerly* wait for the patch that
>> removes existing driver files :)
> 
> The next version of the exynos cpufreq cleanup patches are being
> prepared. But exynos4x12 cpufreq driver will not be included for
> cleanup since the boost frequency bindings need more work.

After you send next patchset, I'll rebase it and resend patchset to support exynos3250 cpufreq.

Thanks,
Chanwoo Choi

[PATCH 0/4] cpufreq: Use cpufreq-cpu0 driver for Exynos3250

[Chanwoo Choi]

Hi Thomas,

On 06/13/2014 04:00 PM, Thomas Abraham wrote:
> On Fri, Jun 13, 2014 at 12:06 PM, Viresh Kumar <viresh.kumar@linaro.org> wrote:
>> cpufreq at vger.kernel.org is dead now. Anyway you should be using linux-pm
>> instead.
>>
>> On 13 June 2014 11:38, Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>> This patchset use cpufreq-cpu0 driver to support Exynos3250 cpufreq. So, this
>>> patchset is based on following patchset[1] by Thomas Abraham.
>>>  [1] http://www.spinics.net/lists/linux-samsung-soc/msg31593.html
>>>
>>> Chanwoo Choi (4):
>>>   clk: samsung: exynos3250: Use cpu-clock provider type to support cpufreq
>>>   clk: samsung: Add support for cpu clocks of Exynos3250
>>>   Documentation: devicetree: Add cpu clock configuration data binding for Exynos3250
>>>   ARM: dts: Exynos: Add cpu clock table and armclk divider table for Exynos3250
>>>
>>>  .../devicetree/bindings/clock/exynos3250-clock.txt | 32 ++++++++++++++++++++++
>>>  arch/arm/boot/dts/exynos3250.dtsi                  | 28 +++++++++++++++++++
>>>  drivers/clk/samsung/clk-cpu.c                      | 31 +++++++++++++++++----
>>>  drivers/clk/samsung/clk-exynos3250.c               | 14 +++++++---
>>>  4 files changed, 96 insertions(+), 9 deletions(-)
>>
>> Nothing really cpufreq specific. Would *eagerly* wait for the patch that
>> removes existing driver files :)
> 
> The next version of the exynos cpufreq cleanup patches are being
> prepared. But exynos4x12 cpufreq driver will not be included for
> cleanup since the boost frequency bindings need more work.

After you send next patchset, I'll rebase it and resend patchset to support exynos3250 cpufreq.

Thanks,
Chanwoo Choi