From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47973) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzgYY-0008I0-4H for qemu-devel@nongnu.org; Wed, 25 Jun 2014 02:19:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WzgYM-0002aH-Ku for qemu-devel@nongnu.org; Wed, 25 Jun 2014 02:19:42 -0400 Received: from mail-wi0-x233.google.com ([2a00:1450:400c:c05::233]:41051) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WzgYM-0002aA-EE for qemu-devel@nongnu.org; Wed, 25 Jun 2014 02:19:30 -0400 Received: by mail-wi0-f179.google.com with SMTP id cc10so1842951wib.0 for ; Tue, 24 Jun 2014 23:19:27 -0700 (PDT) Sender: Paolo Bonzini Message-ID: <53AA69E7.8050406@redhat.com> Date: Wed, 25 Jun 2014 08:19:19 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <1403662641-28526-1-git-send-email-tiejun.chen@intel.com> In-Reply-To: <1403662641-28526-1-git-send-email-tiejun.chen@intel.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tiejun Chen , anthony.perard@citrix.com, stefano.stabellini@eu.citrix.com, mst@redhat.com, Kelly.Zytaruk@amd.com Cc: peter.maydell@linaro.org, xen-devel@lists.xensource.com, allen.m.kay@intel.com, qemu-devel@nongnu.org, anthony@codemonkey.ws, yang.z.zhang@intel.com Il 25/06/2014 04:17, Tiejun Chen ha scritto: > * Don't set that ISA class property, instead, just fake this ISA bridge > with 00:1f.0. How are you going to make this work for Q35 or another PCIe machine that already has an ISA bridge at 00:1f.0? Paolo From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [v5][PATCH 0/5] xen: add Intel IGD passthrough support Date: Wed, 25 Jun 2014 08:19:19 +0200 Message-ID: <53AA69E7.8050406@redhat.com> References: <1403662641-28526-1-git-send-email-tiejun.chen@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1403662641-28526-1-git-send-email-tiejun.chen@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+gceq-qemu-devel=gmane.org@nongnu.org Sender: qemu-devel-bounces+gceq-qemu-devel=gmane.org@nongnu.org To: Tiejun Chen , anthony.perard@citrix.com, stefano.stabellini@eu.citrix.com, mst@redhat.com, Kelly.Zytaruk@amd.com Cc: peter.maydell@linaro.org, xen-devel@lists.xensource.com, allen.m.kay@intel.com, qemu-devel@nongnu.org, anthony@codemonkey.ws, yang.z.zhang@intel.com List-Id: xen-devel@lists.xenproject.org Il 25/06/2014 04:17, Tiejun Chen ha scritto: > * Don't set that ISA class property, instead, just fake this ISA bridge > with 00:1f.0. How are you going to make this work for Q35 or another PCIe machine that already has an ISA bridge at 00:1f.0? Paolo