From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33686) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X07tV-00060k-Vz for qemu-devel@nongnu.org; Thu, 26 Jun 2014 07:31:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X07tO-0003np-Fo for qemu-devel@nongnu.org; Thu, 26 Jun 2014 07:31:09 -0400 Received: from mx1.redhat.com ([209.132.183.28]:1543) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X07tO-0003nc-7L for qemu-devel@nongnu.org; Thu, 26 Jun 2014 07:31:02 -0400 Message-ID: <53AC0462.8010207@redhat.com> Date: Thu, 26 Jun 2014 13:30:42 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <53AA8ACF.3070101@redhat.com> <20140625084835.GF32652@redhat.com> <53AA8E7D.809@intel.com> <20140625090925.GH32652@redhat.com> <53AA9480.1010005@intel.com> <53AA96DF.6070501@redhat.com> <53AA9B58.6050803@intel.com> <53AA9C4E.9070506@redhat.com> <53ABE551.3080407@intel.com> <53ABF00E.6000309@redhat.com> <20140626112603.GC21685@redhat.com> In-Reply-To: <20140626112603.GC21685@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [v5][PATCH 0/5] xen: add Intel IGD passthrough support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: peter.maydell@linaro.org, xen-devel@lists.xensource.com, stefano.stabellini@eu.citrix.com, allen.m.kay@intel.com, Kelly.Zytaruk@amd.com, qemu-devel@nongnu.org, anthony.perard@citrix.com, anthony@codemonkey.ws, yang.z.zhang@intel.com, "Chen, Tiejun" Il 26/06/2014 13:26, Michael S. Tsirkin ha scritto: > On Thu, Jun 26, 2014 at 12:03:58PM +0200, Paolo Bonzini wrote: >> Il 26/06/2014 11:18, Chen, Tiejun ha scritto: >>> >>>> >>>> - offsets 0x0000..0x0fff map to configuration space of the host MCH >>>> >>> >>> Are you saying the config space in the video device? >> >> No, I am saying in a new BAR, or at some magic offset of an existing MMIO >> BAR. >> >> Paolo > > I think v5 goes a bit overboard and overrides too many registers, > driver likely needs much less. > > But IMHO retro-fitting this into PIIX is where the problem is. > We could invent 1000 ways to do this, all of varying levels of > ugliness. > > But why don't we start by more or less cleanly emulating what the driver > needs? If we start with Q35 - it shouldn't be hard to tweak it's MCH to > add the necessary config space, right? > > I know xen doesn't support q35 now but it's opensource :) > > I think that's a good step 1. We can do PV hacks on top if we > decide they aren't too painful. I don't think it's a PV hack. It should be this way in real hardware too (not exactly _this_ hack, but at least no improper relationship among IGD/MCH/PCH). Once you add nested virtualization and nested device assignment to the mix, hacking subsystem IDs simply does not scale. Paolo From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [v5][PATCH 0/5] xen: add Intel IGD passthrough support Date: Thu, 26 Jun 2014 13:30:42 +0200 Message-ID: <53AC0462.8010207@redhat.com> References: <53AA8ACF.3070101@redhat.com> <20140625084835.GF32652@redhat.com> <53AA8E7D.809@intel.com> <20140625090925.GH32652@redhat.com> <53AA9480.1010005@intel.com> <53AA96DF.6070501@redhat.com> <53AA9B58.6050803@intel.com> <53AA9C4E.9070506@redhat.com> <53ABE551.3080407@intel.com> <53ABF00E.6000309@redhat.com> <20140626112603.GC21685@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20140626112603.GC21685@redhat.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+gceq-qemu-devel=gmane.org@nongnu.org Sender: qemu-devel-bounces+gceq-qemu-devel=gmane.org@nongnu.org To: "Michael S. Tsirkin" Cc: peter.maydell@linaro.org, xen-devel@lists.xensource.com, stefano.stabellini@eu.citrix.com, allen.m.kay@intel.com, Kelly.Zytaruk@amd.com, qemu-devel@nongnu.org, anthony.perard@citrix.com, anthony@codemonkey.ws, yang.z.zhang@intel.com, "Chen, Tiejun" List-Id: xen-devel@lists.xenproject.org Il 26/06/2014 13:26, Michael S. Tsirkin ha scritto: > On Thu, Jun 26, 2014 at 12:03:58PM +0200, Paolo Bonzini wrote: >> Il 26/06/2014 11:18, Chen, Tiejun ha scritto: >>> >>>> >>>> - offsets 0x0000..0x0fff map to configuration space of the host MCH >>>> >>> >>> Are you saying the config space in the video device? >> >> No, I am saying in a new BAR, or at some magic offset of an existing MMIO >> BAR. >> >> Paolo > > I think v5 goes a bit overboard and overrides too many registers, > driver likely needs much less. > > But IMHO retro-fitting this into PIIX is where the problem is. > We could invent 1000 ways to do this, all of varying levels of > ugliness. > > But why don't we start by more or less cleanly emulating what the driver > needs? If we start with Q35 - it shouldn't be hard to tweak it's MCH to > add the necessary config space, right? > > I know xen doesn't support q35 now but it's opensource :) > > I think that's a good step 1. We can do PV hacks on top if we > decide they aren't too painful. I don't think it's a PV hack. It should be this way in real hardware too (not exactly _this_ hack, but at least no improper relationship among IGD/MCH/PCH). Once you add nested virtualization and nested device assignment to the mix, hacking subsystem IDs simply does not scale. Paolo