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([2601:646:c200:1ef2:34eb:b0f2:33fb:284c]) by smtp.gmail.com with ESMTPSA id j23sm6983176pfe.95.2019.11.08.19.32.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Nov 2019 19:32:56 -0800 (PST) Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable From: Andy Lutomirski Mime-Version: 1.0 (1.0) Subject: Re: [patch 4/9] x86/io: Speedup schedule out of I/O bitmap user Date: Fri, 8 Nov 2019 19:32:55 -0800 Message-Id: <53B49BD3-6F9C-4A78-B203-1BD53034014D@amacapital.net> References: Cc: Andy Lutomirski , Peter Zijlstra , LKML , x86@kernel.org, Stephen Hemminger , Willy Tarreau , Juergen Gross , Sean Christopherson , Linus Torvalds , "H. Peter Anvin" In-Reply-To: To: Thomas Gleixner X-Mailer: iPhone Mail (17A878) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Nov 8, 2019, at 3:45 PM, Thomas Gleixner wrote: >=20 > =EF=BB=BFOn Fri, 8 Nov 2019, Andy Lutomirski wrote: >>> On 11/7/19 6:08 AM, Thomas Gleixner wrote: >>> On Thu, 7 Nov 2019, Thomas Gleixner wrote: >>>> Just that I can't add the storage to tss_struct due to the VMX insanity= of >>>> setting TSS limit hard to 0x67 on vmexit instead of restoring the host >>>> value. >>>=20 >>> Well, I can. The build bugon in vmx.c is just bogus. >>=20 >> SDM vol 3 27.5.2 says the BUILD_BUG_ON is right. Or am I >> misunderstanding you? >>=20 >> I'm reasonably confident that the TSS limit is indeed 0x67 after VM >> exit, and I wrote the existing code that tries to optimize this to avoid >> LTR when not needed. >=20 > The BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 =3D=3D 0x67) in the VMX code is bogu= s in > two aspects: >=20 > 1) This wants to be in generic x86 code I think disagree. The only thing special about 0x67 is that VMX hard codes i= t. It=E2=80=99s specifically a VMX-ism. So I think the VMX code should indee= d assert that 0x67 is a safe value. >=20 > 2) The IO_BITMAP_OFFSET is not the right thing to check because it makes > asssumptions about the layout of tss_struct. Nothing requires that the > I/O bitmap is placed right after x86_tss, which is the hardware mandated= > tss structure. It pointlessly makes restrictions on the struct > tss_struct layout. I agree with this. >=20 > The proper thing to check is: >=20 > - Offset of x86_tss in tss_struct is 0 > - Size of x86_tss =3D=3D 0x68 >=20 > We already have the page alignment sanity check off TSS in > cpu_entry_area.c. That's where this should have gone into in the first > place. >=20 > Thanks, >=20 > tglx