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Subject: Re: [Qemu-devel] [PATCH 09/15] target-tricore: Add instructions of
 SRRS and SLRO opcode format.
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To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org

On 07/07/2014 11:13 AM, Bastian Koppelmann wrote:
> +/* Functions for load/save to/from memory */
> +#define OP_MEM_INDIRECT(insn)                                             \
> +static inline void gen_indirect_##insn(DisasContext *ctx, TCGv r1, TCGv r2, \
> +                                       int16_t con)                       \
> +{                                                                         \
> +    TCGv temp = tcg_temp_new();                                           \
> +    TCGv tempPC = tcg_const_i32(ctx->pc);                                 \
> +    tcg_gen_addi_tl(temp, r2, con);                                         \
> +    tcg_gen_qemu_##insn(r1, temp, ctx->mem_idx);                            \
> +    tcg_temp_free(tempPC);                                                \
> +    tcg_temp_free(temp);                                                  \
> +}
> +OP_MEM_INDIRECT(ld8s)
> +OP_MEM_INDIRECT(ld8u)
> +OP_MEM_INDIRECT(ld16s)
> +OP_MEM_INDIRECT(ld16u)
> +OP_MEM_INDIRECT(ld32s)
> +OP_MEM_INDIRECT(ld32u)

Please just rearrange all of your memory operations to use the new TCGMemOp
enumeration and the common tcg_gen_qemu_{ld,st}_tl functions.

I nearly suggested that for patch 8, but it's quite obvious here.

tempPC is unused here.

Why call this "indirect"?  A better term would be "offset".


r~