From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47423) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X9rRS-0005d3-KY for qemu-devel@nongnu.org; Wed, 23 Jul 2014 03:58:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1X9rRJ-0006PQ-94 for qemu-devel@nongnu.org; Wed, 23 Jul 2014 03:58:26 -0400 Received: from mail-we0-x229.google.com ([2a00:1450:400c:c03::229]:45452) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1X9rRI-0006PK-VQ for qemu-devel@nongnu.org; Wed, 23 Jul 2014 03:58:17 -0400 Received: by mail-we0-f169.google.com with SMTP id u56so769769wes.0 for ; Wed, 23 Jul 2014 00:58:16 -0700 (PDT) Sender: Paolo Bonzini Message-ID: <53CF6B12.5070700@redhat.com> Date: Wed, 23 Jul 2014 09:58:10 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <1406044070-25667-1-git-send-email-tamlokveer@gmail.com> <1406044070-25667-2-git-send-email-tamlokveer@gmail.com> In-Reply-To: <1406044070-25667-2-git-send-email-tamlokveer@gmail.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/3] intel-iommu: introduce Intel IOMMU (VT-d) emulation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Le Tan , qemu-devel@nongnu.org Cc: Jan Kiszka , Alex Williamson , Knut Omang , Anthony Liguori , "Michael S. Tsirkin" Il 22/07/2014 17:47, Le Tan ha scritto: > +static inline void define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val, > + uint64_t wmask, uint64_t w1cmask) > +{ > + *((uint64_t *)&s->csr[addr]) = val; All these casts are not endian-safe. Please use ldl_le_p, ldq_le_p, stl_le_p, stq_le_p. > + *((uint64_t *)&s->wmask[addr]) = wmask; > + *((uint64_t *)&s->w1cmask[addr]) = w1cmask; > +} > + > +static inline void define_quad_wo(IntelIOMMUState *s, hwaddr addr, > + uint64_t mask) > +{ > + *((uint64_t *)&s->womask[addr]) = mask; > +} > + > +static inline void define_long(IntelIOMMUState *s, hwaddr addr, uint32_t val, > + uint32_t wmask, uint32_t w1cmask) > +{ > + *((uint32_t *)&s->csr[addr]) = val; > + *((uint32_t *)&s->wmask[addr]) = wmask; > + *((uint32_t *)&s->w1cmask[addr]) = w1cmask; > +} > + > +static inline void define_long_wo(IntelIOMMUState *s, hwaddr addr, > + uint32_t mask) > +{ > + *((uint32_t *)&s->womask[addr]) = mask; > +} > + > +/* "External" get/set operations */ > +static inline void set_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val) > +{ > + uint64_t oldval = *((uint64_t *)&s->csr[addr]); > + uint64_t wmask = *((uint64_t *)&s->wmask[addr]); > + uint64_t w1cmask = *((uint64_t *)&s->w1cmask[addr]); > + *((uint64_t *)&s->csr[addr]) = > + ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val); > +} > + > +static inline void set_long(IntelIOMMUState *s, hwaddr addr, uint32_t val) > +{ > + uint32_t oldval = *((uint32_t *)&s->csr[addr]); > + uint32_t wmask = *((uint32_t *)&s->wmask[addr]); > + uint32_t w1cmask = *((uint32_t *)&s->w1cmask[addr]); > + *((uint32_t *)&s->csr[addr]) = > + ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val); > +} > + > +static inline uint64_t get_quad(IntelIOMMUState *s, hwaddr addr) > +{ > + uint64_t val = *((uint64_t *)&s->csr[addr]); > + uint64_t womask = *((uint64_t *)&s->womask[addr]); > + return val & ~womask; > +} > + > + > +static inline uint32_t get_long(IntelIOMMUState *s, hwaddr addr) > +{ > + uint32_t val = *((uint32_t *)&s->csr[addr]); > + uint32_t womask = *((uint32_t *)&s->womask[addr]); > + return val & ~womask; > +} > + > + > + > +/* "Internal" get/set operations */ > +static inline uint64_t __get_quad(IntelIOMMUState *s, hwaddr addr) get_quad_raw? > +{ > + return *((uint64_t *)&s->csr[addr]); > +} > + > +static inline uint32_t __get_long(IntelIOMMUState *s, hwaddr addr) get_long_raw? > +{ > + return *((uint32_t *)&s->csr[addr]); > +} > + > + > +/* val = (val & ~clear) | mask */ > +static inline uint32_t set_mask_long(IntelIOMMUState *s, hwaddr addr, set_clear_long? > + uint32_t clear, uint32_t mask) > +{ > + uint32_t *ptr = (uint32_t *)&s->csr[addr]; > + uint32_t val = (*ptr & ~clear) | mask; > + *ptr = val; > + return val; > +} > + > +/* val = (val & ~clear) | mask */ > +static inline uint64_t set_mask_quad(IntelIOMMUState *s, hwaddr addr, set_clear_quad? > + uint64_t clear, uint64_t mask) > +{ > + uint64_t *ptr = (uint64_t *)&s->csr[addr]; > + uint64_t val = (*ptr & ~clear) | mask; > + *ptr = val; > + return val; > +} > + > +