From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757747AbaGWJie (ORCPT ); Wed, 23 Jul 2014 05:38:34 -0400 Received: from youngberry.canonical.com ([91.189.89.112]:47848 "EHLO youngberry.canonical.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757486AbaGWJid (ORCPT ); Wed, 23 Jul 2014 05:38:33 -0400 Message-ID: <53CF828E.5020201@canonical.com> Date: Wed, 23 Jul 2014 11:38:22 +0200 From: Maarten Lankhorst User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.5.0 MIME-Version: 1.0 To: =?UTF-8?B?Q2hyaXN0aWFuIEvDtm5pZw==?= , Daniel Vetter CC: =?UTF-8?B?Q2hyaXN0aWFuIEvDtm5pZw==?= , Thomas Hellstrom , nouveau , LKML , dri-devel , Ben Skeggs , "Deucher, Alexander" Subject: Re: [Nouveau] [PATCH 09/17] drm/radeon: use common fence implementation for fences References: <20140709093124.11354.3774.stgit@patser> <53CE6AFA.1060807@vodafone.de> <53CE84AA.9030703@amd.com> <53CE8A57.2000803@vodafone.de> <53CF58FB.8070609@canonical.com> <53CF5B9F.1050800@amd.com> <53CF5EFE.6070307@canonical.com> <53CF63C2.7070407@vodafone.de> <53CF6622.6060803@amd.com> <53CF699D.9070902@canonical.com> <53CF6B18.5070107@vodafone.de> <53CF7035.2060808@amd.com> <53CF7191.2090008@canonical.com> <53CF765E.7020802@vodafone.de> <53CF8010.9060809@amd.com> <53CF822E.7050601@amd.com> In-Reply-To: <53CF822E.7050601@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org op 23-07-14 11:36, Christian König schreef: > Am 23.07.2014 11:30, schrieb Daniel Vetter: >> On Wed, Jul 23, 2014 at 11:27 AM, Christian König >> wrote: >>> You submit a job to the hardware and then block the job to wait for radeon >>> to be finished? Well than this would indeed require a hardware reset, but >>> wouldn't that make the whole problem even worse? >>> >>> I mean currently we block one userspace process to wait for other hardware >>> to be finished with a buffer, but what you are describing here blocks the >>> whole hardware to wait for other hardware which in the end blocks all >>> userspace process accessing the hardware. >> There is nothing new here with prime - if one context hangs the gpu it >> blocks everyone else on i915. >> >>> Talking about alternative approaches wouldn't it be simpler to just offload >>> the waiting to a different kernel or userspace thread? >> Well this is exactly what we'll do once we have the scheduler. But >> this is an orthogonal issue imo. > > Mhm, could have the scheduler first? > > Cause that sounds like reducing the necessary fence interface to just a fence->wait function. You would also lose benefits like having a 'perf timechart' for gpu's. ~Maarten From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maarten Lankhorst Subject: Re: [Nouveau] [PATCH 09/17] drm/radeon: use common fence implementation for fences Date: Wed, 23 Jul 2014 11:38:22 +0200 Message-ID: <53CF828E.5020201@canonical.com> References: <20140709093124.11354.3774.stgit@patser> <53CE6AFA.1060807@vodafone.de> <53CE84AA.9030703@amd.com> <53CE8A57.2000803@vodafone.de> <53CF58FB.8070609@canonical.com> <53CF5B9F.1050800@amd.com> <53CF5EFE.6070307@canonical.com> <53CF63C2.7070407@vodafone.de> <53CF6622.6060803@amd.com> <53CF699D.9070902@canonical.com> <53CF6B18.5070107@vodafone.de> <53CF7035.2060808@amd.com> <53CF7191.2090008@canonical.com> <53CF765E.7020802@vodafone.de> <53CF8010.9060809@amd.com> <53CF822E.7050601@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <53CF822E.7050601@amd.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: =?UTF-8?B?Q2hyaXN0aWFuIEvDtm5pZw==?= , Daniel Vetter Cc: Thomas Hellstrom , nouveau , LKML , dri-devel , Ben Skeggs , "Deucher, Alexander" List-Id: nouveau.vger.kernel.org b3AgMjMtMDctMTQgMTE6MzYsIENocmlzdGlhbiBLw7ZuaWcgc2NocmVlZjoKPiBBbSAyMy4wNy4y MDE0IDExOjMwLCBzY2hyaWViIERhbmllbCBWZXR0ZXI6Cj4+IE9uIFdlZCwgSnVsIDIzLCAyMDE0 IGF0IDExOjI3IEFNLCBDaHJpc3RpYW4gS8O2bmlnCj4+IDxjaHJpc3RpYW4ua29lbmlnQGFtZC5j b20+IHdyb3RlOgo+Pj4gWW91IHN1Ym1pdCBhIGpvYiB0byB0aGUgaGFyZHdhcmUgYW5kIHRoZW4g YmxvY2sgdGhlIGpvYiB0byB3YWl0IGZvciByYWRlb24KPj4+IHRvIGJlIGZpbmlzaGVkPyBXZWxs IHRoYW4gdGhpcyB3b3VsZCBpbmRlZWQgcmVxdWlyZSBhIGhhcmR3YXJlIHJlc2V0LCBidXQKPj4+ IHdvdWxkbid0IHRoYXQgbWFrZSB0aGUgd2hvbGUgcHJvYmxlbSBldmVuIHdvcnNlPwo+Pj4KPj4+ IEkgbWVhbiBjdXJyZW50bHkgd2UgYmxvY2sgb25lIHVzZXJzcGFjZSBwcm9jZXNzIHRvIHdhaXQg Zm9yIG90aGVyIGhhcmR3YXJlCj4+PiB0byBiZSBmaW5pc2hlZCB3aXRoIGEgYnVmZmVyLCBidXQg d2hhdCB5b3UgYXJlIGRlc2NyaWJpbmcgaGVyZSBibG9ja3MgdGhlCj4+PiB3aG9sZSBoYXJkd2Fy ZSB0byB3YWl0IGZvciBvdGhlciBoYXJkd2FyZSB3aGljaCBpbiB0aGUgZW5kIGJsb2NrcyBhbGwK Pj4+IHVzZXJzcGFjZSBwcm9jZXNzIGFjY2Vzc2luZyB0aGUgaGFyZHdhcmUuCj4+IFRoZXJlIGlz IG5vdGhpbmcgbmV3IGhlcmUgd2l0aCBwcmltZSAtIGlmIG9uZSBjb250ZXh0IGhhbmdzIHRoZSBn cHUgaXQKPj4gYmxvY2tzIGV2ZXJ5b25lIGVsc2Ugb24gaTkxNS4KPj4KPj4+IFRhbGtpbmcgYWJv dXQgYWx0ZXJuYXRpdmUgYXBwcm9hY2hlcyB3b3VsZG4ndCBpdCBiZSBzaW1wbGVyIHRvIGp1c3Qg b2ZmbG9hZAo+Pj4gdGhlIHdhaXRpbmcgdG8gYSBkaWZmZXJlbnQga2VybmVsIG9yIHVzZXJzcGFj ZSB0aHJlYWQ/Cj4+IFdlbGwgdGhpcyBpcyBleGFjdGx5IHdoYXQgd2UnbGwgZG8gb25jZSB3ZSBo YXZlIHRoZSBzY2hlZHVsZXIuIEJ1dAo+PiB0aGlzIGlzIGFuIG9ydGhvZ29uYWwgaXNzdWUgaW1v Lgo+Cj4gTWhtLCBjb3VsZCBoYXZlIHRoZSBzY2hlZHVsZXIgZmlyc3Q/Cj4KPiBDYXVzZSB0aGF0 IHNvdW5kcyBsaWtlIHJlZHVjaW5nIHRoZSBuZWNlc3NhcnkgZmVuY2UgaW50ZXJmYWNlIHRvIGp1 c3QgYSBmZW5jZS0+d2FpdCBmdW5jdGlvbi4KWW91IHdvdWxkIGFsc28gbG9zZSBiZW5lZml0cyBs aWtlIGhhdmluZyBhICdwZXJmIHRpbWVjaGFydCcgZm9yIGdwdSdzLgoKfk1hYXJ0ZW4KCl9fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWls aW5nIGxpc3QKZHJpLWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwOi8vbGlzdHMuZnJl ZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg==