From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: Re: [PATCH v9 14/20] x86/VPMU: Add support for PMU register handling on PV guests Date: Tue, 12 Aug 2014 13:55:14 +0100 Message-ID: <53EA2AD2020000780002B9E5@mail.emea.novell.com> References: <1407516946-17833-1-git-send-email-boris.ostrovsky@oracle.com> <1407516946-17833-15-git-send-email-boris.ostrovsky@oracle.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1407516946-17833-15-git-send-email-boris.ostrovsky@oracle.com> Content-Disposition: inline List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Boris Ostrovsky Cc: kevin.tian@intel.com, keir@xen.org, suravee.suthikulpanit@amd.com, andrew.cooper3@citrix.com, tim@xen.org, xen-devel@lists.xen.org, jun.nakajima@intel.com List-Id: xen-devel@lists.xenproject.org >>> On 08.08.14 at 18:55, wrote: > @@ -2556,7 +2564,22 @@ static int emulate_privileged_op(struct cpu_user_regs *regs) > if ( v->arch.debugreg[7] & DR7_ACTIVE_MASK ) > wrmsrl(regs->_ecx, msr_content); > break; > - > + case MSR_P6_PERFCTR0...MSR_P6_PERFCTR1: > + case MSR_P6_EVNTSEL0...MSR_P6_EVNTSEL1: > + case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2: > + case MSR_CORE_PERF_FIXED_CTR_CTRL...MSR_CORE_PERF_GLOBAL_OVF_CTRL: > + if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ) > + vpmu_msr = 1; > + /* FALLTHROUGH */ > + case MSR_AMD_FAM15H_EVNTSEL0...MSR_AMD_FAM15H_PERFCTR5: > + if ( vpmu_msr || > + ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !vpmu_msr) ) Pointlessly complicated right side of the ||: (a || (b && !a)) is the same as (a || b). Meaning this _still_ doesn't achieve what you appear to want, i.e. the set of Intel MSRs continues to also get handled on AMD CPUs. Jan