From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH 6/9] xen: arm: Handle CP14 32-bit register accesses from userspace Date: Tue, 09 Sep 2014 16:45:58 -0700 Message-ID: <540F9136.3080903@linaro.org> References: <1410279730.8217.238.camel@kazak.uk.xensource.com> <1410279788-27167-6-git-send-email-ian.campbell@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1410279788-27167-6-git-send-email-ian.campbell@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell , xen-devel@lists.xen.org Cc: tim@xen.org, stefano.stabellini@eu.citrix.com List-Id: xen-devel@lists.xenproject.org Hi Ian, On 09/09/14 09:23, Ian Campbell wrote: > Accesses to these from 32-bit userspace would cause a hypervisor exception > (host crash) when running a 64-bit kernel, which is worked around by the fix to > XSA-102. On 32-bit kernels they would be implemented as RAZ/WI which is > incorrect but harmless. > > Update as follows: > - DBGDSCRINT should be R/O. > - DBGDSCREXT should be EL1 only. > - DBGOSLAR is RO and EL1 only. > - DBGVCR, DBGB[VC]R*, DBGW[VC]R*, and DBGOSDLR are EL1 only. > > DBGDIDR and DBGDSCRINT are accessible from EL0 if DBGDSCRext.UDCCdis. Since we > emulate that as RAZ/WI we allow access. Shall we just set DBGDSCRext.UDCCdis to avoid taking care of EL0 access? Regards, -- Julien Grall