>From 0428f396173e458288a5f0e1807033ebe9931ce0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Tue, 9 Sep 2014 10:09:23 +0900 Subject: [PATCH v2 1/2] drm/radeon: Clean up assignment of TTM placement lpfn member for pinning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This sets the lpfn member to 0 instead of the full domain size. TTM uses the full domain size when lpfn is 0. Signed-off-by: Michel Dänzer --- v2: Handle max_offset == 0 correctly drivers/gpu/drm/radeon/radeon_object.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index 908ea541..24c8772 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -307,18 +307,14 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, } radeon_ttm_placement_from_domain(bo, domain); for (i = 0; i < bo->placement.num_placement; i++) { - unsigned lpfn = 0; - /* force to pin into visible video ram */ - if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) - lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; + if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && + (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) + bo->placements[i].lpfn = + bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; else - lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; /* ??? */ - - if (max_offset) - lpfn = min (lpfn, (unsigned)(max_offset >> PAGE_SHIFT)); + bo->placements[i].lpfn = max_offset >> PAGE_SHIFT; - bo->placements[i].lpfn = lpfn; bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; } -- 2.1.0