From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45406) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XRdyL-00060b-3y for qemu-devel@nongnu.org; Wed, 10 Sep 2014 05:14:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XRdyD-0007xB-88 for qemu-devel@nongnu.org; Wed, 10 Sep 2014 05:13:53 -0400 Message-ID: <54101648.5080307@suse.de> Date: Wed, 10 Sep 2014 11:13:44 +0200 From: Alexander Graf MIME-Version: 1.0 References: <1410325413-3660-1-git-send-email-mallard.pierre@gmail.com> <1410325413-3660-2-git-send-email-mallard.pierre@gmail.com> In-Reply-To: <1410325413-3660-2-git-send-email-mallard.pierre@gmail.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 1/3] target-ppc : Add floating point ability to 440x5 PPC CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Pierre Mallard , qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: tommusta@gmail.com On 10.09.14 07:03, Pierre Mallard wrote: > This patch add some floating point operation for PPC440x5. > Compile with PPC440x5_HAVE_FPU enabled in configure extra-cflags > > Signed-off-by: Pierre Mallard Instead of the define, could we just create a new CPU that has these flags enabled? Just call it "440x5-fpu" or so. Alex > --- > target-ppc/translate_init.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 48177ed..b4dedce 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -3897,6 +3897,10 @@ POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) > pcc->init_proc = init_proc_440x5; > pcc->check_pow = check_pow_nocheck; > pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | > +#ifdef PPC440x5_HAVE_FPU > + PPC_FLOAT | PPC_FLOAT_FSQRT | > + PPC_FLOAT_STFIWX | > +#endif > PPC_DCR | PPC_WRTEE | PPC_RFMCI | > PPC_CACHE | PPC_CACHE_ICBI | > PPC_CACHE_DCBZ | PPC_CACHE_DCBA | >