From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:34921)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <tommusta@gmail.com>) id 1XS3W7-0006j4-B3
	for qemu-devel@nongnu.org; Thu, 11 Sep 2014 08:30:36 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <tommusta@gmail.com>) id 1XS3Vy-0005yR-9d
	for qemu-devel@nongnu.org; Thu, 11 Sep 2014 08:30:27 -0400
Message-ID: <541195D2.5070204@gmail.com>
Date: Thu, 11 Sep 2014 07:30:10 -0500
From: Tom Musta <tommusta@gmail.com>
MIME-Version: 1.0
References: <1410325413-3660-1-git-send-email-mallard.pierre@gmail.com>
	<541017CE.1090704@suse.de> <54108742.2000100@gmail.com>
	<CAKODt8zzFB9jinkKXXG6FhqU08BwN3HBLRu=uz1m8nXJLZM3Og@mail.gmail.com>
In-Reply-To: <CAKODt8zzFB9jinkKXXG6FhqU08BwN3HBLRu=uz1m8nXJLZM3Og@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] Enabling floating point
 instruction to 440x5 CPUs
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Pierre Mallard <mallard.pierre@gmail.com>
Cc: qemu-ppc@nongnu.org, Alexander Graf <agraf@suse.de>, qemu-devel@nongnu.org

On 9/10/2014 5:43 PM, Pierre Mallard wrote:
> On Wed, Sep 10, 2014 at 7:15 PM, Tom Musta <tommusta@gmail.com <mailto:tommusta@gmail.com>> wrote:
> 
> 
>     (1) Eliminate the TARGET_PPC64 checks for all six FP Doubleword Integer Conversion instructions.
> 
> 
> There is also fcfids and fcfidus which leads to 8 instructions (fcfid, fcfids, fcfidu, fcfidus and fctid, fctidz, fctidu, fctiduz), is this right ?

You are correct.

> 
> 
>     (2) Defined a new flag for FP Signed Doubleword Conversion instructions (PPC2_FP_CVT_S64).  Use this flag exclusively when defining the opcode tables, e.g.
> 
>     +/* fctidz */
>     +GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
> 
> I'm not sure, I did understand correctly that one, indeed to have the flag check I have to make changes for each of the three instructions (fcfid, fctif, fctidz) at 2 places in translate.c :
> 
> One at the gen_XXXX function definition which is quite straight forward :
> GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
> becomes
> GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
> 
> One in the Opcode Table which requires to use the GEN_HANDLER_E macro for the second type to be taken in account :
> GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64),
> becomes
> GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64)
> 
> is this right ?

Yes.

>  
> 
> 
>     (3) You would have to add the flag to all existing 64-bit CPUs that support floating point.  And of course, to your new 440-w-fpu CPU.
> 
>  
> Pierre