From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38459) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XXUV4-0003Ev-5a for qemu-devel@nongnu.org; Fri, 26 Sep 2014 08:19:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XXUUz-0002RA-2W for qemu-devel@nongnu.org; Fri, 26 Sep 2014 08:19:50 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:38183) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XXUUy-0002Qb-Sl for qemu-devel@nongnu.org; Fri, 26 Sep 2014 08:19:45 -0400 Message-ID: <5425561A.4020301@imgtec.com> Date: Fri, 26 Sep 2014 13:03:38 +0100 From: James Hogan MIME-Version: 1.0 References: <1403882530-47821-1-git-send-email-leon.alrae@imgtec.com> <1403882530-47821-4-git-send-email-leon.alrae@imgtec.com> In-Reply-To: <1403882530-47821-4-git-send-email-leon.alrae@imgtec.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 03/21] target-mips: add SELEQZ and SELNEZ instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Leon Alrae , qemu-devel@nongnu.org Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, aurelien@aurel32.net, rth@twiddle.net Hi Leon, On 27/06/14 16:21, Leon Alrae wrote: > /* MIPS64 MIPS-3D ASE support. */ > #define I16 INSN_MIPS16 > @@ -1209,6 +1215,8 @@ const struct mips_opcode mips_builtin_opcodes[] = > them first. The assemblers uses a hash table based on the > instruction name anyhow. */ > /* name, args, match, mask, pinfo, membership */ > +{"seleqz", "d,v,t", 0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, > +{"selnez", "d,v,t", 0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6}, I don't think these need to be at the beginning of the table since they're normal instructions, unlike "nop" for example which is encoded as a "sll". Otherwise Reviewed-by: James Hogan Cheers James