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Date: Fri, 26 Sep 2014 15:12:09 +0100
From: Leon Alrae <leon.alrae@imgtec.com>
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Subject: Re: [Qemu-devel] [PATCH v3 04/21] target-mips: move LL and SC
	instructions
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To: James Hogan <james.hogan@imgtec.com>, qemu-devel@nongnu.org
Cc: yongbok.kim@imgtec.com, cristian.cuna@imgtec.com, aurelien@aurel32.net, rth@twiddle.net

Hi James,

On 26/09/2014 13:44, James Hogan wrote:
> Hi Leon,
> 
> On 27/06/14 16:21, Leon Alrae wrote:
>> @@ -1215,6 +1217,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
>>     them first.  The assemblers uses a hash table based on the
>>     instruction name anyhow.  */
>>  /* name,    args,	match,	    mask,	pinfo,          	membership */
>> +{"ll",      "t,o(b)",   0x7c000036, 0xfc00003f, LDD|RD_b|WR_t,        0, I32R6},
>> +{"sc",      "t,o(b)",   0x7c000026, 0xfc00003f, LDD|RD_b|WR_t,        0, I32R6},
> 
> Doesn't bit 6 need to be 0 too for these, so mask should be 0xfc00007f?

Yes, good spot.

> Again, do these strictly have to be at the beginning? I know sc aliases
> dmod.g, but that's right at the end of the table.
> 
>> @@ -15121,7 +15144,8 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
>>              break;
>>          case OPC_DDIV_G_2E ... OPC_DDIVU_G_2E:
>>          case OPC_DMULT_G_2E ... OPC_DMULTU_G_2E:
>> -        case OPC_DMOD_G_2E ... OPC_DMODU_G_2E:
>> +        case OPC_DMODU_G_2E:
>> +            check_insn_opc_removed(ctx, ISA_MIPS32R6);
> 
> AFAICT you remove this check_insn_opc_removed line again in patch 6, so
> I don't think you need to add it here.

Yeah, I wrote this line before I decided to split SPECIAL* into separate
functions. I will remove it as it is not needed.

Thanks,
Leon