From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Mon, 29 Sep 2014 10:14:52 +0200 Subject: [U-Boot] [PATCH v3 4/5] imx: mx6: Checking PLL2 PFD0 and PFD2 for periph_clk before PFD reset In-Reply-To: <1410229021-2995-4-git-send-email-B37916@freescale.com> References: <1410229021-2995-1-git-send-email-B37916@freescale.com> <1410229021-2995-4-git-send-email-B37916@freescale.com> Message-ID: <542914FC.1060903@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 09/09/2014 04:17, Ye.Li wrote: > Checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR > register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source, > do not reset this PFD to avoid system hang. Customers may set this > in DDR script or use BT_FREQ to select low freq boot. > > Signed-off-by: Ye.Li > --- Applied to u-boot-imx, thanks ! Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================