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Date: Mon, 29 Sep 2014 12:31:00 +0200
From: Jan Kiszka <jan.kiszka@siemens.com>
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Subject: Re: [Qemu-devel] [PATCH v7 00/11] target-arm: Parts of the AArch64
 EL2/3 exception model
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To: Peter Maydell <peter.maydell@linaro.org>, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: Rob Herring <rob.herring@linaro.org>, Peter Crosthwaite <peter.crosthwaite@xilinx.com>, Fabian Aggeler <aggelerf@ethz.ch>, Alexander Graf <agraf@suse.de>, QEMU Developers <qemu-devel@nongnu.org>, Paolo Bonzini <pbonzini@redhat.com>, Greg Bellows <greg.bellows@linaro.org>, Sergey Fedorov <serge.fdrv@gmail.com>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, Christoffer Dall <christoffer.dall@linaro.org>, Richard Henderson <rth@twiddle.net>

On 2014-09-26 17:23, Peter Maydell wrote:
> On 26 September 2014 09:08, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
>> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>>
>> Hi,
>>
>> This is a second round of AArch64 EL2/3 patches working on the exception
>> model. Among other things adding HVC/SMC, interrupt routing to EL2/3 and
>> Virtual IRQs/FIQs. The VIRQ/VFIQ support only adds the external signal
>> delivery method.
>>
>> This conflicts slightly with the PSCI emulation patches that Rob posted.
>> A rebase should be trivial, hooking in the PSCI emulation calls in the
>> HVC/SMC code.
> 
> Thanks. I've applied these to target-arm.next, with
> some minor fixups to account for the cpu-exec
> refactoring. Pushed to my git repo if you want
> to grab it before I get round to doing a pullreq:
> git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.next
> 
> (I would still have preferred if we'd just implemented
> the interrupt routing right to start with but in
> the interests of making progress I'll let that pass.)

Sorry for hijacking the thread, but it seems related: These bits address
AArch64, but what is the status of AArch32 /wrt hyp mode emulation?
After playing with the "fast" model, I would be glad to find such
support in QEMU rather sooner than later.

Thanks,
Jan

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