From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?B?QW5kcmVhcyBCaWXDn21hbm4=?= Date: Sat, 25 Oct 2014 02:46:33 +0200 Subject: [U-Boot] [PATCH v1 03/10] arm, at91: add missing ddr2 cr register MPDDRC_CR_EBISHARE define In-Reply-To: <1412142894-997-4-git-send-email-hs@denx.de> References: <1412142894-997-1-git-send-email-hs@denx.de> <1412142894-997-4-git-send-email-hs@denx.de> Message-ID: <544AF2E9.8050609@googlemail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Dear Heiko, On 01.10.14 07:54, Heiko Schocher wrote: > Signed-off-by: Heiko Schocher > Cc: Andreas Bie?mann > Cc: Bo Shen > --- > arch/arm/include/asm/arch-at91/atmel_mpddrc.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h > index 5741f6e..bd403d2 100644 > --- a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h > +++ b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h > @@ -57,6 +57,7 @@ int ddr2_init(const unsigned int ram_address, > #define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8) > #define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9) > #define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12) > +#define ATMEL_MPDDRC_CR_EBISHARE (0x1 << 16) 'EBISHARE' is much more expressive, but the datasheet (sama5d34) names this bit 'DQMS'. How about DQMS_SHARED? > #define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17) > #define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20) > #define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21) >