From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kumar Gala Date: Fri, 16 Sep 2011 09:57:23 -0500 Subject: [U-Boot] [PATCH] powerpc/85xx: Refactor P2041RDB to use common p_corenet files In-Reply-To: <1314745472-20920-3-git-send-email-galak@kernel.crashing.org> References: <1314745472-20920-1-git-send-email-galak@kernel.crashing.org> <1314745472-20920-2-git-send-email-galak@kernel.crashing.org> <1314745472-20920-3-git-send-email-galak@kernel.crashing.org> Message-ID: <5459DE9F-C992-444A-8047-F3DDBC5C749A@kernel.crashing.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Aug 30, 2011, at 6:04 PM, Kumar Gala wrote: > The P2041RDB has almost identical setup for TLB, LAWS, and PCI with > other P-Series CoreNet platforms. > > The only difference between P2041RDB & P3041DS/P4080DS/P5020DS is the > CPLD vs PIXIS FPGA which we can handle via some simple #ifdefs in the > TLB and LAW setup tables. > > Signed-off-by: Kumar Gala > --- > board/freescale/common/Makefile | 1 + > board/freescale/common/p_corenet/law.c | 5 ++ > board/freescale/common/p_corenet/tlb.c | 7 ++ > board/freescale/p2041rdb/Makefile | 3 - > board/freescale/p2041rdb/law.c | 37 ---------- > board/freescale/p2041rdb/pci.c | 39 ---------- > board/freescale/p2041rdb/tlb.c | 123 -------------------------------- > 7 files changed, 13 insertions(+), 202 deletions(-) > delete mode 100644 board/freescale/p2041rdb/law.c > delete mode 100644 board/freescale/p2041rdb/pci.c > delete mode 100644 board/freescale/p2041rdb/tlb.c applied to 85xx 'next' - k