From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH 08/21] KVM: x86: Reset FPU state during reset Date: Wed, 05 Nov 2014 15:55:40 +0100 Message-ID: <545A3A6C.3010302@redhat.com> References: <1414922101-17626-1-git-send-email-namit@cs.technion.ac.il> <1414922101-17626-9-git-send-email-namit@cs.technion.ac.il> <545A1264.5030002@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Nadav Amit , kvm@vger.kernel.org To: Nadav Amit Return-path: Received: from mail-wg0-f44.google.com ([74.125.82.44]:50039 "EHLO mail-wg0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755128AbaKEOzo (ORCPT ); Wed, 5 Nov 2014 09:55:44 -0500 Received: by mail-wg0-f44.google.com with SMTP id x12so1122795wgg.3 for ; Wed, 05 Nov 2014 06:55:43 -0800 (PST) In-Reply-To: Sender: kvm-owner@vger.kernel.org List-ID: On 05/11/2014 14:20, Nadav Amit wrote: >> > Actually it shouldn't be after INIT. XCR0 is not mentioned explic= itly=20 >> > in Table 9-1 of the SDM (IA-32 Processor States Following Power-up= ,=20 >> > Reset, or INIT), but since MSR_IA32_XSS is not specified, I think = XCR0=20 >> > should fall under "All other MSRs=94. >=20 > I should have given a reference, since Intel SDM is a wild place - se= e section 2.6 =93EXTENDED CONTROL REGISTERS (INCLUDING XCR0)=94 : "Afte= r reset, all bits (except bit 0) in XCR0 are cleared to zero, XCR0[0] i= s set to 1." Yes, I found that, but INIT is not reset. :) Reset is typically handled by userspace in the case of KVM. kvm_vcpu_reset is only called by KVM when you get an INIT interrupt, in kvm_accept_apic_events. Paolo