From: Clemens Ladisch <clemens@ladisch.de>
To: thomas chen <tchen61@gmail.com>, alsa-devel@alsa-project.org
Subject: Re: I2S frame configuration
Date: Mon, 08 Dec 2014 18:01:32 +0100 [thread overview]
Message-ID: <5485D96C.3020900@ladisch.de> (raw)
In-Reply-To: <5485C5CA.8030402@gmail.com>
thomas chen wrote:
> I am working on a ALSA interface to a particular codec over I2S
>
> the audio stream format is a bit peculiar...
>
> there are 24 BCLK cycle between transition of FSYNC... howver, there are only 16 bit that are valid
>
> bit 0: ignore
> bit 1-16: valid pcm data (MSB....LSB)
> bit 17-23: ignore
This is the 'original' I²S format. The format where the sample begins
with the 1st BCLK usually is called left-justified (and uses the
opposite FSYNC polarity).
Having ignored bits is common. (Typically, there are 32 BCLK cycles per
sample.)
In ASoC, this would be SND_SOC_DAIFMT_I2S and SND_SOC_DAIFMT_LEFT_J.
Regards,
Clemens
next prev parent reply other threads:[~2014-12-08 17:01 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-12-08 15:37 I2S frame configuration thomas chen
2014-12-08 17:01 ` Clemens Ladisch [this message]
2014-12-08 18:03 ` thomas chen
2014-12-08 19:37 ` Lars-Peter Clausen
2014-12-09 13:51 ` thomas chen
2014-12-09 15:12 ` Lars-Peter Clausen
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