From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ed White <edmund.h.white@intel.com>
Subject: Re: [PATCH 00/11] Alternate p2m: support multiple
 copies of host p2m
Date: Thu, 15 Jan 2015 09:28:07 -0800
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To: Jan Beulich <JBeulich@suse.com>, Tamas K Lengyel <tamas.lengyel@zentific.com>
Cc: Keir Fraser <keir@xen.org>, Ian Campbell <ian.campbell@citrix.com>, Andrew Cooper <andrew.cooper3@citrix.com>, Tim Deegan <tim@xen.org>, "xen-devel@lists.xen.org" <xen-devel@lists.xen.org>, Ian Jackson <ian.jackson@eu.citrix.com>
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On 01/15/2015 12:16 AM, Jan Beulich wrote:
>>>> On 14.01.15 at 18:35, <edmund.h.white@intel.com> wrote:
>> On 01/14/2015 03:28 AM, Tamas K Lengyel wrote:
>>> At the mem_access trap point you can swap in an altp2m where the
>>> gfn->mfn mapping is the one where the breakpoints are hidden,
>>> singlestep, then swap the original p2m back. While this approach still
>>> has some overhead because of the use of singlestepping, it is going to
>>> be faster then what you currently have to do, which is removing all
>>> breakpoints, singlestep, then put breakpoints back. Now it would just
>>> be a matter of swapping a single pointer.
>>
>> Right. The key observation is that at any single point in time, a given
>> hardware thread can be fetching an instruction or reading data, but not
>> both.
> 
> Fine, as long as an instruction reading itself isn't going to lead to
> a live lock.
> 

That's not how the hardware works. By the time you figure out that the
instruction you are executing reads memory, the instruction itself has
been fetched and decoded. That won't happen again during this execution.

That's true for every CPU I've ever seen, not just Intel ones.

Ed