From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42851) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YDznQ-0003LB-Cf for qemu-devel@nongnu.org; Wed, 21 Jan 2015 13:14:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YDznM-0005rn-Ne for qemu-devel@nongnu.org; Wed, 21 Jan 2015 13:14:28 -0500 Received: from mail-qc0-x22a.google.com ([2607:f8b0:400d:c01::22a]:59438) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YDznM-0005re-Hz for qemu-devel@nongnu.org; Wed, 21 Jan 2015 13:14:24 -0500 Received: by mail-qc0-f170.google.com with SMTP id p6so12308608qcv.1 for ; Wed, 21 Jan 2015 10:14:23 -0800 (PST) Sender: Richard Henderson Message-ID: <54BFEC7C.1000400@twiddle.net> Date: Wed, 21 Jan 2015 10:14:20 -0800 From: Richard Henderson MIME-Version: 1.0 References: <1421863489-7716-1-git-send-email-kbastian@mail.uni-paderborn.de> <1421863489-7716-2-git-send-email-kbastian@mail.uni-paderborn.de> In-Reply-To: <1421863489-7716-2-git-send-email-kbastian@mail.uni-paderborn.de> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/4] target-tricore: target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bastian Koppelmann , qemu-devel@nongnu.org On 01/21/2015 10:04 AM, Bastian Koppelmann wrote: > Signed-off-by: Bastian Koppelmann > --- > target-tricore/translate.c | 276 +++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 276 insertions(+) > > diff --git a/target-tricore/translate.c b/target-tricore/translate.c > index def7f4a..da8ecbc 100644 > --- a/target-tricore/translate.c > +++ b/target-tricore/translate.c > @@ -4778,6 +4778,279 @@ static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx) > tcg_temp_free(n); > } > > +static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx) > +{ > + uint32_t op2; > + int r1, r2, r3; > + uint32_t n; > + > + TCGv temp, temp2; > + > + r1 = MASK_OP_RR1_S1(ctx->opcode); > + r2 = MASK_OP_RR1_S2(ctx->opcode); > + r3 = MASK_OP_RR1_D(ctx->opcode); > + n = MASK_OP_RR1_N(ctx->opcode); > + op2 = MASK_OP_RR1_OP2(ctx->opcode); > + > + temp = tcg_temp_new(); > + temp2 = tcg_temp_new(); > + > + switch (op2) { > + case OPC2_32_RR1_MUL_Q_32: > + if (n == 0) { > + tcg_gen_muls2_tl(temp, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); > + /* reset v bit */ > + tcg_gen_movi_tl(cpu_PSW_V, 0); > + } else { > + tcg_gen_muls2_tl(temp, temp2, cpu_gpr_d[r1], cpu_gpr_d[r2]); > + tcg_gen_shli_tl(temp2, temp2, n); > + tcg_gen_shri_tl(temp, temp, 31); Yes, n is supposed to be either 0 or 1. But mixing n with a constant is confusing. Either hard-code 1 here (perhaps preferred?), or write 32-n. > + case OPC2_32_RR1_MUL_Q_64: > + if (n == 0) { > + tcg_gen_muls2_tl(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], > + cpu_gpr_d[r2]); > + /* reset v bit */ > + tcg_gen_movi_tl(cpu_PSW_V, 0); > + } else { > + tcg_gen_muls2_tl(temp, temp2, cpu_gpr_d[r1], cpu_gpr_d[r2]); > + tcg_gen_shli_tl(temp2, temp2, n); > + tcg_gen_shli_tl(cpu_gpr_d[r3], temp, n); > + tcg_gen_shri_tl(temp, temp, 31); > + tcg_gen_or_tl(cpu_gpr_d[r3+1], temp, temp2); I do wonder about just using 64-bit arithmetic here, instead of emulating a 64-bit shift. > + /* overflow only occours if r1 = r2 = 0x8000 */ > + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r3+1], > + 0x80000000); > + tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); > + } > + /* calc sv overflow bit */ > + tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); > + /* calc av overflow bit */ > + tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r3+1], cpu_gpr_d[r3+1]); > + tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r3+1], cpu_PSW_AV); > + /* calc sav overflow bit */ > + tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); > + break; > + case OPC2_32_RR1_MUL_Q_32_L: > + tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); > + if (n == 0) { > + tcg_gen_muls2_tl(temp, temp2, temp, cpu_gpr_d[r1]); > + tcg_gen_shli_tl(cpu_gpr_d[r3], temp2, 16); > + tcg_gen_shri_tl(temp, temp, 16); > + tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); Similarly. > + /* reset v bit */ > + tcg_gen_movi_tl(cpu_PSW_V, 0); > + } else { > + tcg_gen_muls2_tl(temp, temp2, temp, cpu_gpr_d[r1]); > + tcg_gen_shli_tl(cpu_gpr_d[r3], temp2, 17); > + tcg_gen_shri_tl(temp, temp, 15); > + tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); > + /* overflow only occours if r1 = r2 = 0x8000 */ > + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r3], > + 0x80000000); > + tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); > + } > + /* calc sv overflow bit */ > + tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); > + /* calc av overflow bit */ > + tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r3], cpu_gpr_d[r3]); > + tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r3], cpu_PSW_AV); > + /* calc sav overflow bit */ > + tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); > + break; > + case OPC2_32_RR1_MUL_Q_64_L: > + tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); > + if (n == 0) { > + tcg_gen_muls2_tl(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], > + temp); > + /* reset v bit */ > + tcg_gen_movi_tl(cpu_PSW_V, 0); > + } else { > + tcg_gen_muls2_tl(temp, temp2, cpu_gpr_d[r1], temp); > + tcg_gen_shli_tl(temp2, temp2, n); > + tcg_gen_shli_tl(cpu_gpr_d[r3], temp, n); > + tcg_gen_shri_tl(temp, temp, 31); > + tcg_gen_or_tl(cpu_gpr_d[r3+1], temp, temp2); > + /* overflow only occours if r1 = r2 = 0x8000 */ > + tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r3+1], > + 0x80000000); > + tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); > + } > + /* calc sv overflow bit */ > + tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); > + /* calc av overflow bit */ > + tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r3+1], cpu_gpr_d[r3+1]); > + tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r3+1], cpu_PSW_AV); > + /* calc sav overflow bit */ > + tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); > + break; > + case OPC2_32_RR1_MUL_Q_32_U: > + tcg_gen_shri_tl(temp, cpu_gpr_d[r2], 16); > + tcg_gen_ext16s_tl(temp, temp); Use an arithmetic shift and you don't need the sign-extend. There's an awful lot of replication in here. I think a few different subroutines are warrented. r~