From: Richard Henderson <rth@twiddle.net>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 2/4] target-tricore: Add instructions of RR2 opcode format
Date: Wed, 21 Jan 2015 10:16:22 -0800 [thread overview]
Message-ID: <54BFECF6.2030700@twiddle.net> (raw)
In-Reply-To: <1421863489-7716-3-git-send-email-kbastian@mail.uni-paderborn.de>
On 01/21/2015 10:04 AM, Bastian Koppelmann wrote:
> + case OPC2_32_RR2_MUL_32:
> + gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
> + break;
> + case OPC2_32_RR2_MUL_64:
> + gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
> + cpu_gpr_d[r2]);
> + break;
What happend to flags computation?
r~
next prev parent reply other threads:[~2015-01-21 18:16 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-01-21 18:04 [Qemu-devel] [PATCH 0/4] TriCore add instructions of RR1, RR2, RRPW and RRR opcode format Bastian Koppelmann
2015-01-21 18:04 ` [Qemu-devel] [PATCH 1/4] target-tricore: target-tricore: Add instructions of RR1 opcode format, that have 0x93 as first opcode Bastian Koppelmann
2015-01-21 18:14 ` Richard Henderson
2015-01-21 18:04 ` [Qemu-devel] [PATCH 2/4] target-tricore: Add instructions of RR2 opcode format Bastian Koppelmann
2015-01-21 18:16 ` Richard Henderson [this message]
2015-01-22 14:58 ` Bastian Koppelmann
2015-01-21 18:04 ` [Qemu-devel] [PATCH 3/4] target-tricore: Add instructions of RRPW " Bastian Koppelmann
2015-01-21 18:57 ` Richard Henderson
2015-01-21 18:04 ` [Qemu-devel] [PATCH 4/4] target-tricore: Add instructions of RRR " Bastian Koppelmann
2015-01-21 19:45 ` Richard Henderson
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