From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH 4/4] VMX: replace plain numbers Date: Thu, 22 Jan 2015 14:01:14 +0000 Message-ID: <54C110BA020000780005829D@mail.emea.novell.com> References: <54C10EE1020000780005827E@mail.emea.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part4570DDBA.1__=" Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YEIJw-0004w5-Fq for xen-devel@lists.xenproject.org; Thu, 22 Jan 2015 14:01:16 +0000 In-Reply-To: <54C10EE1020000780005827E@mail.emea.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel Cc: Kevin Tian , Eddie Dong , Jun Nakajima List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part4570DDBA.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline ... making the code better document itself. No functional change intended. Signed-off-by: Jan Beulich --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -1406,7 +1406,9 @@ static void __vmx_inject_exception(int t * VM entry]", PRM Vol. 3, 22.6.1 (Interruptibility State). */ =20 - intr_fields =3D (INTR_INFO_VALID_MASK | (type<<8) | trap); + intr_fields =3D INTR_INFO_VALID_MASK | + MASK_INSR(type, INTR_INFO_INTR_TYPE_MASK) | + MASK_INSR(trap, INTR_INFO_VECTOR_MASK); if ( error_code !=3D HVM_DELIVER_NO_ERROR_CODE ) { __vmwrite(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); intr_fields |=3D INTR_INFO_DELIVER_CODE_MASK; @@ -1430,7 +1432,9 @@ void vmx_inject_extint(int trap, uint8_t PIN_BASED_VM_EXEC_CONTROL); if ( pin_based_cntrl & PIN_BASED_EXT_INTR_MASK ) { nvmx_enqueue_n2_exceptions (v,=20 - INTR_INFO_VALID_MASK | (X86_EVENTTYPE_EXT_INTR<<8) | trap, + INTR_INFO_VALID_MASK | + MASK_INSR(X86_EVENTTYPE_EXT_INTR, INTR_INFO_INTR_TYPE_MASK)= | + MASK_INSR(trap, INTR_INFO_VECTOR_MASK), HVM_DELIVER_NO_ERROR_CODE, source); return; } @@ -1449,7 +1453,9 @@ void vmx_inject_nmi(void) PIN_BASED_VM_EXEC_CONTROL); if ( pin_based_cntrl & PIN_BASED_NMI_EXITING ) { nvmx_enqueue_n2_exceptions (v,=20 - INTR_INFO_VALID_MASK | (X86_EVENTTYPE_NMI<<8) | TRAP_nmi, + INTR_INFO_VALID_MASK | + MASK_INSR(X86_EVENTTYPE_NMI, INTR_INFO_INTR_TYPE_MASK) | + MASK_INSR(TRAP_nmi, INTR_INFO_VECTOR_MASK), HVM_DELIVER_NO_ERROR_CODE, hvm_intsrc_nmi); return; } @@ -1487,7 +1493,7 @@ static void vmx_inject_trap(struct hvm_t if ( guest_cpu_user_regs()->eflags & X86_EFLAGS_TF ) { __restore_debug_registers(curr); - write_debugreg(6, read_debugreg(6) | 0x4000); + write_debugreg(6, read_debugreg(6) | DR_STEP); } if ( cpu_has_monitor_trap_flag ) break; @@ -1502,7 +1508,8 @@ static void vmx_inject_trap(struct hvm_t } =20 if ( unlikely(intr_info & INTR_INFO_VALID_MASK) && - (((intr_info >> 8) & 7) =3D=3D X86_EVENTTYPE_HW_EXCEPTION) ) + (MASK_EXTR(intr_info, INTR_INFO_INTR_TYPE_MASK) =3D=3D + X86_EVENTTYPE_HW_EXCEPTION) ) { _trap.vector =3D hvm_combine_hw_exceptions( (uint8_t)intr_info, _trap.vector); @@ -1517,7 +1524,9 @@ static void vmx_inject_trap(struct hvm_t nvmx_intercepts_exception(curr, _trap.vector, _trap.error_code) = ) { nvmx_enqueue_n2_exceptions (curr,=20 - INTR_INFO_VALID_MASK | (_trap.type<<8) | _trap.vector, + INTR_INFO_VALID_MASK | + MASK_INSR(_trap.type, INTR_INFO_INTR_TYPE_MASK) | + MASK_INSR(_trap.vector, INTR_INFO_VECTOR_MASK), _trap.error_code, hvm_intsrc_none); return; } @@ -1976,8 +1985,11 @@ static int vmx_cr_access(unsigned long e } case VMX_CONTROL_REG_ACCESS_TYPE_LMSW: { unsigned long value =3D curr->arch.hvm_vcpu.guest_cr[0]; - /* LMSW can: (1) set bits 0-3; (2) clear bits 1-3. */ - value =3D (value & ~0xe) | ((exit_qualification >> 16) & 0xf); + + /* LMSW can (1) set PE; (2) set or clear MP, EM, and TS. */ + value =3D (value & ~(X86_CR0_MP|X86_CR0_EM|X86_CR0_TS)) | + (VMX_CONTROL_REG_ACCESS_DATA(exit_qualification) & + (X86_CR0_PE|X86_CR0_MP|X86_CR0_EM|X86_CR0_TS)); HVMTRACE_LONG_1D(LMSW, value); return hvm_set_cr0(value); } @@ -2803,7 +2815,7 @@ void vmx_vmexit_handler(struct cpu_user_ */ __vmread(EXIT_QUALIFICATION, &exit_qualification); HVMTRACE_1D(TRAP_DEBUG, exit_qualification); - write_debugreg(6, exit_qualification | 0xffff0ff0); + write_debugreg(6, exit_qualification | DR_STATUS_RESERVED_ONE)= ; if ( !v->domain->debugger_attached || cpu_has_monitor_trap_fla= g ) goto exit_and_crash; domain_pause_for_debugger(); @@ -2872,8 +2884,8 @@ void vmx_vmexit_handler(struct cpu_user_ hvm_inject_page_fault(regs->error_code, exit_qualification); break; case TRAP_nmi: - if ( (intr_info & INTR_INFO_INTR_TYPE_MASK) !=3D - (X86_EVENTTYPE_NMI << 8) ) + if ( MASK_EXTR(intr_info, INTR_INFO_INTR_TYPE_MASK) !=3D + X86_EVENTTYPE_NMI ) goto exit_and_crash; HVMTRACE_0D(NMI); /* Already handled above. */ @@ -2924,7 +2936,8 @@ void vmx_vmexit_handler(struct cpu_user_ * - TSW is a vectored event due to a SW exception or SW = interrupt. */ inst_len =3D ((source !=3D 3) || /* CALL, IRET, or JMP? */ - (idtv_info & (1u<<10))) /* IntrType > 3? */ + (MASK_EXTR(idtv_info, INTR_INFO_INTR_TYPE_MASK) + > 3)) /* IntrType > 3? */ ? get_instruction_length() /* Safe: SDM 3B 23.2.4 */ : 0; if ( (source =3D=3D 3) && (idtv_info & INTR_INFO_DELIVER_CODE_MASK= ) ) __vmread(IDT_VECTORING_ERROR_CODE, &ecode); --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -1272,7 +1272,7 @@ static void sync_exception_state(struct=20 if ( !(nvmx->intr.intr_info & INTR_INFO_VALID_MASK) ) return; =20 - switch ( (nvmx->intr.intr_info & INTR_INFO_INTR_TYPE_MASK) >> 8 ) + switch ( MASK_EXTR(nvmx->intr.intr_info, INTR_INFO_INTR_TYPE_MASK) ) { case X86_EVENTTYPE_EXT_INTR: /* rename exit_reason to EXTERNAL_INTERRUPT */ @@ -1327,10 +1327,10 @@ static void nvmx_update_apicv(struct vcp ppr =3D vlapic_set_ppr(vlapic); WARN_ON((ppr & 0xf0) !=3D (vector & 0xf0)); =20 - status =3D vector << 8; + status =3D vector << VMX_GUEST_INTR_STATUS_SVI_OFFSET; rvi =3D vlapic_has_pending_irq(v); if ( rvi !=3D -1 ) - status |=3D rvi & 0xff; + status |=3D rvi & VMX_GUEST_INTR_STATUS_SUBFIELD_BITMASK; =20 __vmwrite(GUEST_INTR_STATUS, status); } @@ -2161,7 +2161,8 @@ int nvmx_n2_vmexit_handler(struct cpu_us case EXIT_REASON_EXCEPTION_NMI: { unsigned long intr_info; - u32 valid_mask =3D (X86_EVENTTYPE_HW_EXCEPTION << 8) | + u32 valid_mask =3D MASK_INSR(X86_EVENTTYPE_HW_EXCEPTION, + INTR_INFO_INTR_TYPE_MASK) | INTR_INFO_VALID_MASK; u64 exec_bitmap; int vector; @@ -2350,8 +2351,8 @@ int nvmx_n2_vmexit_handler(struct cpu_us u32 mask =3D 0; =20 __vmread(EXIT_QUALIFICATION, &exit_qualification); - cr =3D exit_qualification & 0xf; - write =3D (exit_qualification >> 4) & 3; + cr =3D VMX_CONTROL_REG_ACCESS_NUM(exit_qualification); + write =3D VMX_CONTROL_REG_ACCESS_TYPE(exit_qualification); /* also according to guest exec_control */ ctrl =3D __n2_exec_control(v); =20 @@ -2443,8 +2444,9 @@ int nvmx_n2_vmexit_handler(struct cpu_us u64 cr0_gh_mask =3D __get_vvmcs(nvcpu->nv_vvmcx, = CR0_GUEST_HOST_MASK); =20 __vmread(CR0_READ_SHADOW, &old_val); - old_val &=3D 0xf; - val =3D (exit_qualification >> 16) & 0xf; + old_val &=3D X86_CR0_PE|X86_CR0_MP|X86_CR0_EM|X86_CR0_TS; + val =3D VMX_CONTROL_REG_ACCESS_DATA(exit_qualification) & + (X86_CR0_PE|X86_CR0_MP|X86_CR0_EM|X86_CR0_TS); changed_bits =3D old_val ^ val; if ( changed_bits & cr0_gh_mask ) nvcpu->nv_vmexit_pending =3D 1; --- a/xen/include/asm-x86/hvm/vmx/vmx.h +++ b/xen/include/asm-x86/hvm/vmx/vmx.h @@ -207,8 +207,10 @@ static inline unsigned long pi_get_pir(s # define VMX_CONTROL_REG_ACCESS_TYPE_MOV_FROM_CR 1 # define VMX_CONTROL_REG_ACCESS_TYPE_CLTS 2 # define VMX_CONTROL_REG_ACCESS_TYPE_LMSW 3 - /* 10:8 - general purpose register operand */ + /* 11:8 - general purpose register operand */ #define VMX_CONTROL_REG_ACCESS_GPR(eq) (((eq) >> 8) & 0xf) + /* 31:16 - LMSW source data */ +#define VMX_CONTROL_REG_ACCESS_DATA(eq) ((uint32_t)(eq) >> 16) =20 /* * Access Rights --=__Part4570DDBA.1__= Content-Type: text/plain; name="VMX-literals.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="VMX-literals.patch" VMX: replace plain numbers=0A=0A... making the code better document = itself. No functional change=0Aintended.=0A=0ASigned-off-by: Jan Beulich = =0A=0A--- a/xen/arch/x86/hvm/vmx/vmx.c=0A+++ b/xen/arch/= x86/hvm/vmx/vmx.c=0A@@ -1406,7 +1406,9 @@ static void __vmx_inject_exceptio= n(int t=0A * VM entry]", PRM Vol. 3, 22.6.1 (Interruptibility = State).=0A */=0A =0A- intr_fields =3D (INTR_INFO_VALID_MASK | = (type<<8) | trap);=0A+ intr_fields =3D INTR_INFO_VALID_MASK |=0A+ = MASK_INSR(type, INTR_INFO_INTR_TYPE_MASK) |=0A+ = MASK_INSR(trap, INTR_INFO_VECTOR_MASK);=0A if ( error_code !=3D = HVM_DELIVER_NO_ERROR_CODE ) {=0A __vmwrite(VM_ENTRY_EXCEPTION_ERROR= _CODE, error_code);=0A intr_fields |=3D INTR_INFO_DELIVER_CODE_MASK= ;=0A@@ -1430,7 +1432,9 @@ void vmx_inject_extint(int trap, uint8_t=0A = PIN_BASED_VM_EXEC_CONTROL);=0A if = ( pin_based_cntrl & PIN_BASED_EXT_INTR_MASK ) {=0A nvmx_enqueue= _n2_exceptions (v, =0A- INTR_INFO_VALID_MASK | (X86_EVENTTYPE= _EXT_INTR<<8) | trap,=0A+ INTR_INFO_VALID_MASK |=0A+ = MASK_INSR(X86_EVENTTYPE_EXT_INTR, INTR_INFO_INTR_TYPE_MASK) |=0A+ = MASK_INSR(trap, INTR_INFO_VECTOR_MASK),=0A = HVM_DELIVER_NO_ERROR_CODE, source);=0A return;=0A = }=0A@@ -1449,7 +1453,9 @@ void vmx_inject_nmi(void)=0A = PIN_BASED_VM_EXEC_CONTROL);=0A if ( pin_based_cntr= l & PIN_BASED_NMI_EXITING ) {=0A nvmx_enqueue_n2_exceptions = (v, =0A- INTR_INFO_VALID_MASK | (X86_EVENTTYPE_NMI<<8) | = TRAP_nmi,=0A+ INTR_INFO_VALID_MASK |=0A+ = MASK_INSR(X86_EVENTTYPE_NMI, INTR_INFO_INTR_TYPE_MASK) |=0A+ = MASK_INSR(TRAP_nmi, INTR_INFO_VECTOR_MASK),=0A HVM_DELIVER_N= O_ERROR_CODE, hvm_intsrc_nmi);=0A return;=0A }=0A@@ = -1487,7 +1493,7 @@ static void vmx_inject_trap(struct hvm_t=0A if = ( guest_cpu_user_regs()->eflags & X86_EFLAGS_TF )=0A {=0A = __restore_debug_registers(curr);=0A- write_debugreg(6, = read_debugreg(6) | 0x4000);=0A+ write_debugreg(6, read_debugreg(= 6) | DR_STEP);=0A }=0A if ( cpu_has_monitor_trap_flag )=0A = break;=0A@@ -1502,7 +1508,8 @@ static void vmx_inject_trap(stru= ct hvm_t=0A }=0A =0A if ( unlikely(intr_info & INTR_INFO_VALID_MASK= ) &&=0A- (((intr_info >> 8) & 7) =3D=3D X86_EVENTTYPE_HW_EXCEPTION)= )=0A+ (MASK_EXTR(intr_info, INTR_INFO_INTR_TYPE_MASK) =3D=3D=0A+ = X86_EVENTTYPE_HW_EXCEPTION) )=0A {=0A _trap.vector =3D = hvm_combine_hw_exceptions(=0A (uint8_t)intr_info, _trap.vector)= ;=0A@@ -1517,7 +1524,9 @@ static void vmx_inject_trap(struct hvm_t=0A = nvmx_intercepts_exception(curr, _trap.vector, _trap.error_code) )=0A = {=0A nvmx_enqueue_n2_exceptions (curr, =0A- INTR_INFO_= VALID_MASK | (_trap.type<<8) | _trap.vector,=0A+ INTR_INFO_VALID= _MASK |=0A+ MASK_INSR(_trap.type, INTR_INFO_INTR_TYPE_MASK) = |=0A+ MASK_INSR(_trap.vector, INTR_INFO_VECTOR_MASK),=0A = _trap.error_code, hvm_intsrc_none);=0A return;=0A }=0A@@ = -1976,8 +1985,11 @@ static int vmx_cr_access(unsigned long e=0A }=0A = case VMX_CONTROL_REG_ACCESS_TYPE_LMSW: {=0A unsigned long value = =3D curr->arch.hvm_vcpu.guest_cr[0];=0A- /* LMSW can: (1) set bits = 0-3; (2) clear bits 1-3. */=0A- value =3D (value & ~0xe) | = ((exit_qualification >> 16) & 0xf);=0A+=0A+ /* LMSW can (1) set PE; = (2) set or clear MP, EM, and TS. */=0A+ value =3D (value & = ~(X86_CR0_MP|X86_CR0_EM|X86_CR0_TS)) |=0A+ (VMX_CONTROL_REG_= ACCESS_DATA(exit_qualification) &=0A+ (X86_CR0_PE|X86_CR0_M= P|X86_CR0_EM|X86_CR0_TS));=0A HVMTRACE_LONG_1D(LMSW, value);=0A = return hvm_set_cr0(value);=0A }=0A@@ -2803,7 +2815,7 @@ void = vmx_vmexit_handler(struct cpu_user_=0A */=0A = __vmread(EXIT_QUALIFICATION, &exit_qualification);=0A = HVMTRACE_1D(TRAP_DEBUG, exit_qualification);=0A- write_debugreg(= 6, exit_qualification | 0xffff0ff0);=0A+ write_debugreg(6, = exit_qualification | DR_STATUS_RESERVED_ONE);=0A if ( = !v->domain->debugger_attached || cpu_has_monitor_trap_flag )=0A = goto exit_and_crash;=0A domain_pause_for_debugger();=0A@@ = -2872,8 +2884,8 @@ void vmx_vmexit_handler(struct cpu_user_=0A = hvm_inject_page_fault(regs->error_code, exit_qualification);=0A = break;=0A case TRAP_nmi:=0A- if ( (intr_info & = INTR_INFO_INTR_TYPE_MASK) !=3D=0A- (X86_EVENTTYPE_NMI << = 8) )=0A+ if ( MASK_EXTR(intr_info, INTR_INFO_INTR_TYPE_MASK) = !=3D=0A+ X86_EVENTTYPE_NMI )=0A goto = exit_and_crash;=0A HVMTRACE_0D(NMI);=0A /* Already = handled above. */=0A@@ -2924,7 +2936,8 @@ void vmx_vmexit_handler(struct = cpu_user_=0A * - TSW is a vectored event due to a SW exception = or SW interrupt.=0A */=0A inst_len =3D ((source !=3D 3) = || /* CALL, IRET, or JMP? */=0A- (idtv_info & = (1u<<10))) /* IntrType > 3? */=0A+ (MASK_EXTR(idtv_info,= INTR_INFO_INTR_TYPE_MASK)=0A+ > 3)) /* IntrType > 3? = */=0A ? get_instruction_length() /* Safe: SDM 3B 23.2.4 */ : = 0;=0A if ( (source =3D=3D 3) && (idtv_info & INTR_INFO_DELIVER_CODE= _MASK) )=0A __vmread(IDT_VECTORING_ERROR_CODE, &ecode);=0A--- = a/xen/arch/x86/hvm/vmx/vvmx.c=0A+++ b/xen/arch/x86/hvm/vmx/vvmx.c=0A@@ = -1272,7 +1272,7 @@ static void sync_exception_state(struct =0A if ( = !(nvmx->intr.intr_info & INTR_INFO_VALID_MASK) )=0A return;=0A = =0A- switch ( (nvmx->intr.intr_info & INTR_INFO_INTR_TYPE_MASK) >> 8 = )=0A+ switch ( MASK_EXTR(nvmx->intr.intr_info, INTR_INFO_INTR_TYPE_MASK)= )=0A {=0A case X86_EVENTTYPE_EXT_INTR:=0A /* rename = exit_reason to EXTERNAL_INTERRUPT */=0A@@ -1327,10 +1327,10 @@ static void = nvmx_update_apicv(struct vcp=0A ppr =3D vlapic_set_ppr(vlapic);=0A = WARN_ON((ppr & 0xf0) !=3D (vector & 0xf0));=0A =0A- status = =3D vector << 8;=0A+ status =3D vector << VMX_GUEST_INTR_STATUS_SVI_= OFFSET;=0A rvi =3D vlapic_has_pending_irq(v);=0A if ( rvi = !=3D -1 )=0A- status |=3D rvi & 0xff;=0A+ status = |=3D rvi & VMX_GUEST_INTR_STATUS_SUBFIELD_BITMASK;=0A =0A = __vmwrite(GUEST_INTR_STATUS, status);=0A }=0A@@ -2161,7 +2161,8 @@ int = nvmx_n2_vmexit_handler(struct cpu_us=0A case EXIT_REASON_EXCEPTION_NMI:= =0A {=0A unsigned long intr_info;=0A- u32 valid_mask = =3D (X86_EVENTTYPE_HW_EXCEPTION << 8) |=0A+ u32 valid_mask =3D = MASK_INSR(X86_EVENTTYPE_HW_EXCEPTION,=0A+ = INTR_INFO_INTR_TYPE_MASK) |=0A INTR_INFO_VALID_MAS= K;=0A u64 exec_bitmap;=0A int vector;=0A@@ -2350,8 +2351,8 = @@ int nvmx_n2_vmexit_handler(struct cpu_us=0A u32 mask =3D 0;=0A = =0A __vmread(EXIT_QUALIFICATION, &exit_qualification);=0A- = cr =3D exit_qualification & 0xf;=0A- write =3D (exit_qualification = >> 4) & 3;=0A+ cr =3D VMX_CONTROL_REG_ACCESS_NUM(exit_qualification)= ;=0A+ write =3D VMX_CONTROL_REG_ACCESS_TYPE(exit_qualification);=0A = /* also according to guest exec_control */=0A ctrl =3D = __n2_exec_control(v);=0A =0A@@ -2443,8 +2444,9 @@ int nvmx_n2_vmexit_handle= r(struct cpu_us=0A u64 cr0_gh_mask =3D __get_vvmcs(nvcpu->n= v_vvmcx, CR0_GUEST_HOST_MASK);=0A =0A __vmread(CR0_READ_SHA= DOW, &old_val);=0A- old_val &=3D 0xf;=0A- = val =3D (exit_qualification >> 16) & 0xf;=0A+ old_val &=3D = X86_CR0_PE|X86_CR0_MP|X86_CR0_EM|X86_CR0_TS;=0A+ val =3D = VMX_CONTROL_REG_ACCESS_DATA(exit_qualification) &=0A+ = (X86_CR0_PE|X86_CR0_MP|X86_CR0_EM|X86_CR0_TS);=0A = changed_bits =3D old_val ^ val;=0A if ( changed_bits & = cr0_gh_mask )=0A nvcpu->nv_vmexit_pending =3D 1;=0A--- = a/xen/include/asm-x86/hvm/vmx/vmx.h=0A+++ b/xen/include/asm-x86/hvm/vmx/vmx= .h=0A@@ -207,8 +207,10 @@ static inline unsigned long pi_get_pir(s=0A # = define VMX_CONTROL_REG_ACCESS_TYPE_MOV_FROM_CR 1=0A # define VMX_CONTROL_RE= G_ACCESS_TYPE_CLTS 2=0A # define VMX_CONTROL_REG_ACCESS_TYPE_LMSW = 3=0A- /* 10:8 - general purpose register operand */=0A+ /* 11:8 - = general purpose register operand */=0A #define VMX_CONTROL_REG_ACCESS_GPR(e= q) (((eq) >> 8) & 0xf)=0A+ /* 31:16 - LMSW source data */=0A+#define = VMX_CONTROL_REG_ACCESS_DATA(eq) ((uint32_t)(eq) >> 16)=0A =0A /*=0A * = Access Rights=0A --=__Part4570DDBA.1__= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel --=__Part4570DDBA.1__=--