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Wed, 10 Apr 2019 00:40:17 +0000 Received: from DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a]) by DB3PR0502MB3980.eurprd05.prod.outlook.com ([fe80::6072:43be:7c2d:103a%3]) with mapi id 15.20.1792.009; Wed, 10 Apr 2019 00:40:17 +0000 From: Yongseok Koh To: "jerinjacobk@gmail.com" , Pavan Nikhilesh CC: Thomas Monjalon , dev , Jerin Jacob Thread-Topic: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags Thread-Index: AQHU7IUKSU3sF3w6YEmoHpDY1RrqtKY0kuQA Date: Wed, 10 Apr 2019 00:40:17 +0000 Message-ID: <54C87541-6DC7-4CAF-850B-8F7A4BF1C9BD@mellanox.com> References: <20190318164949.2357-1-jerinj@marvell.com> <20190406142737.20091-1-jerinj@marvell.com> <20190406142737.20091-2-jerinj@marvell.com> In-Reply-To: <20190406142737.20091-2-jerinj@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [209.116.155.178] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 2610afe5-5312-445f-9e45-08d6bd4d1a55 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600139)(711020)(4605104)(4618075)(2017052603328)(7193020); SRVR:DB3PR0502MB4092; x-ms-traffictypediagnostic: DB3PR0502MB4092: x-ld-processed: a652971c-7d2e-4d9b-a6a4-d149256f461b,ExtAddr x-microsoft-antispam-prvs: x-forefront-prvs: 00032065B2 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(136003)(366004)(39860400002)(346002)(396003)(376002)(189003)(199004)(51914003)(36756003)(8936002)(25786009)(6486002)(81156014)(81166006)(6436002)(229853002)(14454004)(97736004)(54906003)(110136005)(2616005)(256004)(316002)(305945005)(476003)(11346002)(7736002)(446003)(71200400001)(2906002)(83716004)(71190400001)(486006)(5660300002)(33656002)(102836004)(2501003)(105586002)(99286004)(478600001)(86362001)(68736007)(6506007)(76176011)(53936002)(6116002)(53546011)(6246003)(6512007)(3846002)(82746002)(106356001)(66066001)(26005)(4326008)(186003); DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0502MB4092; H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: XDpke4keOSUut8dMLWqT8Ld04bSqr6hWQxFDB5PysAuyDBg2i2IgD9RHswsuNNZd/VQ8wWmhn7KN68a79GgzOq27k5uy8KLd6dOJLbt1AmHvE1i085aYcgKxXIwqV31QjRXuPYkpM53sPtr8zCAPPVSPB/mjLuMUK0zgMqBPK3f6Fbcy72TeQeCkZpD2NHS2zPfUmwtAWuySxmnvpDORxR58ZyoXvtUMe3xVJDTAuKrdZQI1oq7lRIQY8AXWYYOc1Wd2dP3LVO0b2NDyo4B5EGHGvDHB8X2pRMVPh5XU1nhqvdIVnueLevnqKb0gdtlRGV1cctV0c76l0QwyI5sMHNU7THVLUaivP16qJG85ifVSsrDTRjelARLY8m6yaTR1WrHOaUsXvw+QM1GlD/DTCUJ7WvQPJ5vkOuodZ7wmTtc= Content-Type: text/plain; charset="us-ascii" Content-ID: <8DD2399796B0B441818B92423E422C00@eurprd05.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2610afe5-5312-445f-9e45-08d6bd4d1a55 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Apr 2019 00:40:17.0433 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB4092 Subject: Re: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > On Apr 6, 2019, at 7:27 AM, jerinjacobk@gmail.com wrote: >=20 > From: Pavan Nikhilesh >=20 > Currently, RTE_* flags are set based on the implementer ID but there migh= t > be some micro arch specific differences from the same vendor > eg. CACHE_LINESIZE. Add support to set micro arch specific flags. >=20 > Signed-off-by: Pavan Nikhilesh > Signed-off-by: Jerin Jacob > --- > config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++----- > 1 file changed, 32 insertions(+), 5 deletions(-) >=20 > diff --git a/config/arm/meson.build b/config/arm/meson.build > index 170a4981a..8de3f3e3a 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -52,12 +52,10 @@ flags_generic =3D [ > ['RTE_USE_C11_MEM_MODEL', true], > ['RTE_CACHE_LINE_SIZE', 128]] > flags_cavium =3D [ > - ['RTE_MACHINE', '"thunderx"'], > ['RTE_CACHE_LINE_SIZE', 128], > ['RTE_MAX_NUMA_NODES', 2], > ['RTE_MAX_LCORE', 96], > - ['RTE_MAX_VFIO_GROUPS', 128], > - ['RTE_USE_C11_MEM_MODEL', false]] > + ['RTE_MAX_VFIO_GROUPS', 128]] > flags_dpaa =3D [ > ['RTE_MACHINE', '"dpaa"'], > ['RTE_USE_C11_MEM_MODEL', true], > @@ -71,6 +69,27 @@ flags_dpaa2 =3D [ > ['RTE_MAX_NUMA_NODES', 1], > ['RTE_MAX_LCORE', 16], > ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] > +flags_default_extra =3D [] > +flags_thunderx_extra =3D [ > + ['RTE_MACHINE', '"thunderx"'], > + ['RTE_USE_C11_MEM_MODEL', false]] > + > +machine_args_generic =3D [ > + ['default', ['-march=3Darmv8-a+crc+crypto']], > + ['native', ['-march=3Dnative']], > + ['0xd03', ['-mcpu=3Dcortex-a53']], > + ['0xd04', ['-mcpu=3Dcortex-a35']], > + ['0xd07', ['-mcpu=3Dcortex-a57']], > + ['0xd08', ['-mcpu=3Dcortex-a72']], > + ['0xd09', ['-mcpu=3Dcortex-a73']], > + ['0xd0a', ['-mcpu=3Dcortex-a75']]] > + > +machine_args_cavium =3D [ > + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], > + ['native', ['-march=3Dnative']], > + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], > + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], > + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] Looks like there's a mistake in rebasing it? You should've removed machine_args_generic and machine_args_cavium in the beginning of this file. Other than that, it looks good to me. BTW, thanks for the patch. I raised this issue before and I was supposed to make the change but you have taken it. Yongseok > ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) > impl_generic =3D ['Generic armv8', flags_generic, machine_args_generic] > @@ -157,8 +176,16 @@ else > endif > foreach marg: machine[2] > if marg[0] =3D=3D impl_pn > - foreach f: marg[1] > - machine_args +=3D f > + foreach flag: marg[1] > + if cc.has_argument(flag) > + machine_args +=3D flag > + endif > + endforeach > + # Apply any extra machine specific flags. > + foreach flag: marg.get(2, flags_default_extra) > + if flag.length() > 0 > + dpdk_conf.set(flag[0], flag[1]) > + endif > endforeach > endif > endforeach > --=20 > 2.21.0 >=20