From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33844) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YGqEF-0005Jt-QJ for qemu-devel@nongnu.org; Thu, 29 Jan 2015 09:37:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YGqEA-00070g-Jz for qemu-devel@nongnu.org; Thu, 29 Jan 2015 09:37:55 -0500 Received: from cantor2.suse.de ([195.135.220.15]:47682 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YGqEA-00070R-De for qemu-devel@nongnu.org; Thu, 29 Jan 2015 09:37:50 -0500 Message-ID: <54CA45BC.8070709@suse.de> Date: Thu, 29 Jan 2015 15:37:48 +0100 From: Alexander Graf MIME-Version: 1.0 References: <1421857131-18539-1-git-send-email-agraf@suse.de> <1421857131-18539-4-git-send-email-agraf@suse.de> <54CA4431.1060606@suse.de> In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 3/4] arm: Add PCIe host bridge in virt machine List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Rob Herring , "Michael S. Tsirkin" , QEMU Developers , Ard Biesheuvel , Claudio Fontana , Alvise Rigo , Stuart Yoder On 29.01.15 15:34, Peter Maydell wrote: > On 29 January 2015 at 14:31, Alexander Graf wrote: >> >> >> On 27.01.15 17:52, Peter Maydell wrote: >>> On 21 January 2015 at 16:18, Alexander Graf wrote: >>>> + /* Map the MMIO window at the same spot in bus and cpu layouts */ >>>> + mmio_alias = g_new0(MemoryRegion, 1); >>>> + mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); >>>> + memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", >>>> + mmio_reg, base_mmio, size_mmio); >>>> + memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias); >>> >>> The comment claims to be mapping the MMIO window twice (in the >>> system memory space and in the PCI mmio address space) but the >>> code only seems to be mapping something into system memory space? >> >> The comment claims to map it at the same spot. It means the offset in >> system memory is the same offset as the one in the mmio window that gets >> exported by the PHB. >> >> The PHB exports a UINT64_MAX MMIO region as id 1. This is basically a >> full window into the PCI address space. What we do here is to map a 1:1 >> window between CPU address space and PCI address space. > > I kind of see, but isn't this just a window from CPU address > space into PCI address space, not vice-versa? Yup, exactly. But PCI devices need to map themselves somewhere into the PCI address space. So if I configure a BAR to live at 0x10000000, it should also show up at 0x10000000 when accessed from the CPU. That's what the mapping above is about. > DMA by PCI devices bus-mastering into system memory must be > being set up elsewhere, I think. Yes, that's a different mechanism that's not implemented yet for GPEX :). On ARM this would happen via SMMU emulation. Alex