From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754937AbbBFJH1 (ORCPT ); Fri, 6 Feb 2015 04:07:27 -0500 Received: from foss.arm.com ([217.140.101.70]:39891 "EHLO usa-sjc-mx-foss1.foss.arm.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751839AbbBFJHT (ORCPT ); Fri, 6 Feb 2015 04:07:19 -0500 X-Greylist: delayed 303 seconds by postgrey-1.27 at vger.kernel.org; Fri, 06 Feb 2015 04:07:19 EST Message-ID: <54D4843E.7060201@arm.com> Date: Fri, 06 Feb 2015 09:07:10 +0000 From: Marc Zyngier Organization: ARM Ltd User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.3.0 MIME-Version: 1.0 To: Brent Wang , Mark Rutland CC: "dan.zhao@hisilicon.com" , "btw@mail.itp.ac.cn" , Catalin Marinas , "wangbinghui@hisilicon.com" , Will Deacon , "huxinwei@huawei.com" , "khilman@linaro.org" , "haojian.zhuang@linaro.org" , "yanhaifeng@gmail.com" , "rob.herring@linaro.org" , "mturquette@linaro.org" , "victor.lixin@hisilicon.com" , "xuwei5@hisilicon.com" , "jh80.chung@samsung.com" , "sledge.yanwei@huawei.com" , "kong.kongxinwei@hisilicon.com" , "heyunlei@huawei.com" , "w.f@huawei.com" , "zhangfei.gao@linaro.org" , "z.liuxinliang@huawei.com" , "devicetree@vger.kernel.org" , Bintian Wang , Pawel Moll , "ijc+devicetree@hellion.org.uk" , "puck.chen@hisilicon.com" , "olof@lixom.net" , "robh+dt@kernel.org" , "linux@arm.linux.org.uk" , "zhenwei.wang@hisilicon.com" , "linux-arm-kernel@lists.infradead.org" , "guodong.xu@linaro.org" , "tomeu.vizoso@collabora.com" , "sboyd@codeaurora.org" , "linux-kernel@vger.kernel.org" , "galak@codeaurora.org" , "xuejiancheng@huawei.com" , "xuyiping@hisilicon.com" , "liguozhu@hisilicon.com" Subject: Re: [PATCH 3/3] arm64: dts: Add dts files for Hisilicon Hi6220 SoC References: <1423128277-10297-1-git-send-email-bintian.wang@huawei.com> <1423128277-10297-4-git-send-email-bintian.wang@huawei.com> <20150205193017.GF20735@leverpostej> In-Reply-To: Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/02/15 08:42, Brent Wang wrote: [...] >> >>> + <0x0 0xf6802000 0x0 0x2000>, /* GICC */ >>> + <0x0 0xf6804000 0x0 0x2000>, /* GICH */ >>> + <0x0 0xf6806000 0x0 0x2000>; /* GICV */ >> >> I guess no-one's bothered to consider 64k pages? >> >> Given GICH and GICV, I hope that this platform is booted at EL2? > Transfer from EL3 to EL1 directly, keep these two just for future use. That's a real shame, as it keeps users away from some key aspects of the ARMv8 architecture. >> >>> + #interrupt-cells = <3>; >>> + #address-cells = <0>; >>> + interrupt-controller; And if you're keeping GICH/GICV, where is the maintenance interrupt? >>> + }; >>> + >>> + >>> + timer { >>> + compatible = "arm,armv8-timer"; >>> + interrupt-parent = <&gic>; >>> + interrupts = <1 13 0xff08>, >>> + <1 14 0xff08>, >>> + <1 11 0xff08>, >>> + <1 10 0xff08>; >>> + clock-frequency = <1200000>; >>> + }; >> >> NAK. Fix your firmware to configure CNTFRQ, on all CPUs. > Fix in next version, maybe it will take some time to change firmware. While you're at it, make sure CNTVOFF_EL2 is set to zero on all CPUs before dropping to EL1. This tends to be overlooked. Thanks, M. -- Jazz is not dead. It just smells funny... From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: Re: [PATCH 3/3] arm64: dts: Add dts files for Hisilicon Hi6220 SoC Date: Fri, 06 Feb 2015 09:07:10 +0000 Message-ID: <54D4843E.7060201@arm.com> References: <1423128277-10297-1-git-send-email-bintian.wang@huawei.com> <1423128277-10297-4-git-send-email-bintian.wang@huawei.com> <20150205193017.GF20735@leverpostej> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Brent Wang , Mark Rutland Cc: "dan.zhao@hisilicon.com" , "btw@mail.itp.ac.cn" , Catalin Marinas , "wangbinghui@hisilicon.com" , Will Deacon , "huxinwei@huawei.com" , "khilman@linaro.org" , "haojian.zhuang@linaro.org" , "yanhaifeng@gmail.com" , "rob.herring@linaro.org" , "mturquette@linaro.org" , "victor.lixin@hisilicon.com" , "xuwei5@hisilicon.com" , "jh80.chung@samsung.com" , "sledge.yanwei@huawei.com" , "kong.kongxinwei@hisilicon.com" , "heyunlei@huawei.com" , "w.f@huawei.com" List-Id: devicetree@vger.kernel.org On 06/02/15 08:42, Brent Wang wrote: [...] >> >>> + <0x0 0xf6802000 0x0 0x2000>, /* GICC */ >>> + <0x0 0xf6804000 0x0 0x2000>, /* GICH */ >>> + <0x0 0xf6806000 0x0 0x2000>; /* GICV */ >> >> I guess no-one's bothered to consider 64k pages? >> >> Given GICH and GICV, I hope that this platform is booted at EL2? > Transfer from EL3 to EL1 directly, keep these two just for future use. That's a real shame, as it keeps users away from some key aspects of the ARMv8 architecture. >> >>> + #interrupt-cells = <3>; >>> + #address-cells = <0>; >>> + interrupt-controller; And if you're keeping GICH/GICV, where is the maintenance interrupt? >>> + }; >>> + >>> + >>> + timer { >>> + compatible = "arm,armv8-timer"; >>> + interrupt-parent = <&gic>; >>> + interrupts = <1 13 0xff08>, >>> + <1 14 0xff08>, >>> + <1 11 0xff08>, >>> + <1 10 0xff08>; >>> + clock-frequency = <1200000>; >>> + }; >> >> NAK. Fix your firmware to configure CNTFRQ, on all CPUs. > Fix in next version, maybe it will take some time to change firmware. While you're at it, make sure CNTVOFF_EL2 is set to zero on all CPUs before dropping to EL1. This tends to be overlooked. Thanks, M. -- Jazz is not dead. It just smells funny... From mboxrd@z Thu Jan 1 00:00:00 1970 From: marc.zyngier@arm.com (Marc Zyngier) Date: Fri, 06 Feb 2015 09:07:10 +0000 Subject: [PATCH 3/3] arm64: dts: Add dts files for Hisilicon Hi6220 SoC In-Reply-To: References: <1423128277-10297-1-git-send-email-bintian.wang@huawei.com> <1423128277-10297-4-git-send-email-bintian.wang@huawei.com> <20150205193017.GF20735@leverpostej> Message-ID: <54D4843E.7060201@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 06/02/15 08:42, Brent Wang wrote: [...] >> >>> + <0x0 0xf6802000 0x0 0x2000>, /* GICC */ >>> + <0x0 0xf6804000 0x0 0x2000>, /* GICH */ >>> + <0x0 0xf6806000 0x0 0x2000>; /* GICV */ >> >> I guess no-one's bothered to consider 64k pages? >> >> Given GICH and GICV, I hope that this platform is booted at EL2? > Transfer from EL3 to EL1 directly, keep these two just for future use. That's a real shame, as it keeps users away from some key aspects of the ARMv8 architecture. >> >>> + #interrupt-cells = <3>; >>> + #address-cells = <0>; >>> + interrupt-controller; And if you're keeping GICH/GICV, where is the maintenance interrupt? >>> + }; >>> + >>> + >>> + timer { >>> + compatible = "arm,armv8-timer"; >>> + interrupt-parent = <&gic>; >>> + interrupts = <1 13 0xff08>, >>> + <1 14 0xff08>, >>> + <1 11 0xff08>, >>> + <1 10 0xff08>; >>> + clock-frequency = <1200000>; >>> + }; >> >> NAK. Fix your firmware to configure CNTFRQ, on all CPUs. > Fix in next version, maybe it will take some time to change firmware. While you're at it, make sure CNTVOFF_EL2 is set to zero on all CPUs before dropping to EL1. This tends to be overlooked. Thanks, M. -- Jazz is not dead. It just smells funny...