From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jaehoon Chung Date: Wed, 25 Feb 2015 18:32:28 +0900 Subject: [U-Boot] [PATCH] mmc: s5p: properly mask SELBASECLK In-Reply-To: <1424728342-5367-1-git-send-email-mreimer@sdgsystems.com> References: <1424728342-5367-1-git-send-email-mreimer@sdgsystems.com> Message-ID: <54ED96AC.6030201@samsung.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi, Matt. You're right, it's wrong masking. Acked-by: Jaehoon Chung Best Regards, Jaehoon Chung On 02/24/2015 06:52 AM, Matt Reimer wrote: > Properly mask SELBASECLK by using an actual mask rather than the > number of bits to shift in order to create the mask. > > Signed-off-by: Matt Reimer > --- > drivers/mmc/s5p_sdhci.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c > index 3899372..0eec731 100644 > --- a/drivers/mmc/s5p_sdhci.c > +++ b/drivers/mmc/s5p_sdhci.c > @@ -30,7 +30,7 @@ static void s5p_sdhci_set_control_reg(struct sdhci_host *host) > sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4); > > val = sdhci_readl(host, SDHCI_CONTROL2); > - val &= SDHCI_CTRL2_SELBASECLK_SHIFT; > + val &= SDHCI_CTRL2_SELBASECLK_MASK(3); > > val |= SDHCI_CTRL2_ENSTAASYNCCLR | > SDHCI_CTRL2_ENCMDCNFMSK | >