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[83.42.57.239]) by smtp.gmail.com with ESMTPSA id v4sm68853731wrw.42.2020.12.31.02.31.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 31 Dec 2020 02:31:32 -0800 (PST) Subject: Re: [PATCH 1/2] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic To: Bin Meng , Peter Maydell , Jean-Christophe Dubois , Alistair Francis , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <1608182913-54603-1-git-send-email-bmeng.cn@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <54a57f94-e0e5-6dfd-2813-a38e374f221c@amsat.org> Date: Thu, 31 Dec 2020 11:31:31 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.0 MIME-Version: 1.0 In-Reply-To: <1608182913-54603-1-git-send-email-bmeng.cn@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -48 X-Spam_score: -4.9 X-Spam_bar: ---- X-Spam_report: (-4.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-3.399, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/17/20 6:28 AM, Bin Meng wrote: > From: Bin Meng > > For the ECSPIx_CONREG register BURST_LENGTH field, the manual says: > > 0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word. > 0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word. > > Current logic uses either s->burst_length or 32, whichever smaller, > to determine how many bits it should read from the tx fifo each time. > For example, for a 48 bit burst length, current logic transfers the > first 32 bit from the first word in the tx fifo, followed by a 16 > bit from the second word in the tx fifo, which is wrong. The correct > logic should be: transfer the first 16 bit from the first word in > the tx fifo, followed by a 32 bit from the second word in the tx fifo. > > With this change, SPI flash can be successfully probed by U-Boot on > imx6 sabrelite board. > > => sf probe > SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB > > Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") > Signed-off-by: Bin Meng > --- > > hw/ssi/imx_spi.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c > index 85c172e..509fb9f 100644 > --- a/hw/ssi/imx_spi.c > +++ b/hw/ssi/imx_spi.c > @@ -178,7 +178,10 @@ static void imx_spi_flush_txfifo(IMXSPIState *s) > > DPRINTF("data tx:0x%08x\n", tx); > > - tx_burst = MIN(s->burst_length, 32); > + tx_burst = s->burst_length % 32; > + if (tx_burst == 0) { > + tx_burst = 32; > + } Or alternatively using ternary operator: tx_burst = (s->burst_length % 32) ?: 32; Reviewed-by: Philippe Mathieu-Daudé > > rx = 0; > >