Re: [PATCH V2 1/5] PCI: tegra: Fix handling BME_CHGED event

From: Vidya Sagar <vidyas@nvidia.com>
To: Om Prakash Singh <omp@nvidia.com>, <kw@linux.com>,
	<helgaas@kernel.org>, <lorenzo.pieralisi@arm.com>,
	<bhelgaas@google.com>, <thierry.reding@gmail.com>,
	<jonathanh@nvidia.com>
Cc: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <kthota@nvidia.com>,
	<mmaddireddy@nvidia.com>
Subject: Re: [PATCH V2 1/5] PCI: tegra: Fix handling BME_CHGED event
Date: Tue, 8 Jun 2021 16:07:17 +0530	[thread overview]
Message-ID: <54fe5d68-9bc9-ce80-3917-49d616802698@nvidia.com> (raw)
In-Reply-To: <20210606082204.14222-2-omp@nvidia.com>

Acked-by: Vidya Sagar <vidyas@nvidia.com>

On 6/6/2021 1:52 PM, Om Prakash Singh wrote:
> In tegra_pcie_ep_hard_irq(), APPL_INTR_STATUS_L0 is stored in val and again
> APPL_INTR_STATUS_L1_0_0 is also stored in val. So when execution reaches
> "if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT)", val is not correct.
> 
> Signed-off-by: Om Prakash Singh <omp@nvidia.com>
> ---
> 
> Changes in V2:
> 	- Update variable naming as per comment from Bjorn Helgaas
> 
>   drivers/pci/controller/dwc/pcie-tegra194.c | 30 +++++++++++-----------
>   1 file changed, 15 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index bafd2c6ab3c2..6f388523bffe 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -615,19 +615,19 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
>   	struct tegra_pcie_dw *pcie = arg;
>   	struct dw_pcie_ep *ep = &pcie->pci.ep;
>   	int spurious = 1;
> -	u32 val, tmp;
> +	u32 status_l0, status_l1, link_status;
>   
> -	val = appl_readl(pcie, APPL_INTR_STATUS_L0);
> -	if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
> -		val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
> -		appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0);
> +	status_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0);
> +	if (status_l0 & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
> +		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
> +		appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);
>   
> -		if (val & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE)
> +		if (status_l1 & APPL_INTR_STATUS_L1_0_0_HOT_RESET_DONE)
>   			pex_ep_event_hot_rst_done(pcie);
>   
> -		if (val & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) {
> -			tmp = appl_readl(pcie, APPL_LINK_STATUS);
> -			if (tmp & APPL_LINK_STATUS_RDLH_LINK_UP) {
> +		if (status_l1 & APPL_INTR_STATUS_L1_0_0_RDLH_LINK_UP_CHGED) {
> +			link_status = appl_readl(pcie, APPL_LINK_STATUS);
> +			if (link_status & APPL_LINK_STATUS_RDLH_LINK_UP) {
>   				dev_dbg(pcie->dev, "Link is up with Host\n");
>   				dw_pcie_ep_linkup(ep);
>   			}
> @@ -636,11 +636,11 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
>   		spurious = 0;
>   	}
>   
> -	if (val & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) {
> -		val = appl_readl(pcie, APPL_INTR_STATUS_L1_15);
> -		appl_writel(pcie, val, APPL_INTR_STATUS_L1_15);
> +	if (status_l0 & APPL_INTR_STATUS_L0_PCI_CMD_EN_INT) {
> +		status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_15);
> +		appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_15);
>   
> -		if (val & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED)
> +		if (status_l1 & APPL_INTR_STATUS_L1_15_CFG_BME_CHGED)
>   			return IRQ_WAKE_THREAD;
>   
>   		spurious = 0;
> @@ -648,8 +648,8 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
>   
>   	if (spurious) {
>   		dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n",
> -			 val);
> -		appl_writel(pcie, val, APPL_INTR_STATUS_L0);
> +			 status_l0);
> +		appl_writel(pcie, status_l0, APPL_INTR_STATUS_L0);
>   	}
>   
>   	return IRQ_HANDLED;
>