From mboxrd@z Thu Jan  1 00:00:00 1970
From: "Jan Beulich" <JBeulich@suse.com>
Subject: Re: [PATCH 3/6] X86: improve psr scheduling code
Date: Mon, 16 Mar 2015 16:53:35 +0000
Message-ID: <5507189F020000780006A6B8@mail.emea.novell.com>
References: <1426241605-4114-1-git-send-email-chao.p.peng@linux.intel.com>
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To: Chao Peng <chao.p.peng@linux.intel.com>
Cc: wei.liu2@citrix.com, Ian.Campbell@citrix.com, stefano.stabellini@eu.citrix.com, andrew.cooper3@citrix.com, Ian.Jackson@eu.citrix.com, xen-devel@lists.xen.org, will.auld@intel.com, keir@xen.org, dgdegra@tycho.nsa.gov
List-Id: xen-devel@lists.xenproject.org

>>> On 13.03.15 at 11:13, <chao.p.peng@linux.intel.com> wrote:
> @@ -1473,11 +1471,10 @@ static void __context_switch(void)
>          }
>          vcpu_restore_fpu_eager(n);
>          n->arch.ctxt_switch_to(n);
> -
> -        if ( psr_cmt_enabled() && n->domain->arch.psr_rmid > 0 )
> -            psr_assoc_rmid(n->domain->arch.psr_rmid);
>      }
>  
> +    psr_ctxt_switch_to(n->domain);

But you now potentially do the MSR write despite it already being
the needed value (e.g. when switching between an idle vCPU and
another one also having RMID zero).

Jan