From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH 1/2] x86/vMSI-X: honor all mask requests Date: Fri, 20 Mar 2015 16:27:29 +0000 Message-ID: <550C5881020000780006C2AE@mail.emea.novell.com> References: <550C5065020000780006C27E@mail.emea.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part1A2E4E61.1__=" Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YYzlk-0004f6-Np for xen-devel@lists.xenproject.org; Fri, 20 Mar 2015 16:27:32 +0000 In-Reply-To: <550C5065020000780006C27E@mail.emea.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: xen-devel Cc: Andrew Cooper , Keir Fraser List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part1A2E4E61.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Commit 74fd0036de ("x86: properly handle MSI-X unmask operation from guests") didn't go far enough: it fixed an issue with unmasking, but left an issue with masking in place: Due to the (late) point in time when qemu requests the hypervisor to set up MSI-X interrupts (which is where the MMIO intercept gets put in place), the hypervisor doesn't see all guest writes, and hence shouldn't make assumptions on the state the virtual MSI-X resources are in. Bypassing the rest of the logic on a guest mask operation leads to [00:04.0] pci_msix_write: Error: Can't update msix entry 1 since MSI-X is = already enabled. which surprisingly enough doesn't lead to the device not working anymore (I didn't dig in deep enough to figure out why that is). But it does prevent the IRQ to be migrated inside the guest, i.e. all interrupts will always arrive in vCPU 0. Signed-off-by: Jan Beulich --- a/xen/arch/x86/hvm/vmsi.c +++ b/xen/arch/x86/hvm/vmsi.c @@ -286,11 +286,11 @@ static int msixtbl_write(struct vcpu *v, goto out; } =20 - /* exit to device model if address/data has been modified */ - if ( test_and_clear_bit(nr_entry, &entry->table_flags) ) + /* Exit to device model when unmasking and address/data got modified. = */ + if ( !(val & PCI_MSIX_VECTOR_BITMASK) && + test_and_clear_bit(nr_entry, &entry->table_flags) ) { - if ( !(val & PCI_MSIX_VECTOR_BITMASK) ) - v->arch.hvm_vcpu.hvm_io.msix_unmask_address =3D address; + v->arch.hvm_vcpu.hvm_io.msix_unmask_address =3D address; goto out; } =20 --=__Part1A2E4E61.1__= Content-Type: text/plain; name="x86-vMSI-X-honor-masking.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="x86-vMSI-X-honor-masking.patch" x86/vMSI-X: honor all mask requests=0A=0ACommit 74fd0036de ("x86: properly = handle MSI-X unmask operation from=0Aguests") didn't go far enough: it = fixed an issue with unmasking, but=0Aleft an issue with masking in place: = Due to the (late) point in time=0Awhen qemu requests the hypervisor to set = up MSI-X interrupts (which is=0Awhere the MMIO intercept gets put in = place), the hypervisor doesn't=0Asee all guest writes, and hence shouldn't = make assumptions on the state=0Athe virtual MSI-X resources are in. = Bypassing the rest of the logic on=0Aa guest mask operation leads = to=0A=0A[00:04.0] pci_msix_write: Error: Can't update msix entry 1 since = MSI-X is already enabled.=0A=0Awhich surprisingly enough doesn't lead to = the device not working=0Aanymore (I didn't dig in deep enough to figure = out why that is). But it=0Adoes prevent the IRQ to be migrated inside the = guest, i.e. all=0Ainterrupts will always arrive in vCPU 0.=0A=0ASigned-off-= by: Jan Beulich =0A=0A--- a/xen/arch/x86/hvm/vmsi.c=0A++= + b/xen/arch/x86/hvm/vmsi.c=0A@@ -286,11 +286,11 @@ static int msixtbl_writ= e(struct vcpu *v,=0A goto out;=0A }=0A =0A- /* exit to = device model if address/data has been modified */=0A- if ( test_and_clea= r_bit(nr_entry, &entry->table_flags) )=0A+ /* Exit to device model when = unmasking and address/data got modified. */=0A+ if ( !(val & PCI_MSIX_VE= CTOR_BITMASK) &&=0A+ test_and_clear_bit(nr_entry, &entry->table_fla= gs) )=0A {=0A- if ( !(val & PCI_MSIX_VECTOR_BITMASK) )=0A- = v->arch.hvm_vcpu.hvm_io.msix_unmask_address =3D address;=0A+ = v->arch.hvm_vcpu.hvm_io.msix_unmask_address =3D address;=0A goto = out;=0A }=0A =0A --=__Part1A2E4E61.1__= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel --=__Part1A2E4E61.1__=--