From mboxrd@z Thu Jan 1 00:00:00 1970 From: York Sun Date: Fri, 20 Mar 2015 17:08:38 -0700 Subject: [U-Boot] [PATCH 20/28] armv8/ls2085ardb: Add support of LS2085ARDB platform In-Reply-To: <1426892467.27998.244.camel@freescale.com> References: <1426783559-26610-1-git-send-email-yorksun@freescale.com> <1426783559-26610-20-git-send-email-yorksun@freescale.com> <1426892467.27998.244.camel@freescale.com> Message-ID: <550CB686.7080607@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 03/20/2015 04:01 PM, Scott Wood wrote: > On Thu, 2015-03-19 at 09:45 -0700, York Sun wrote: >> The LS2080ARDB is a evaluation platform that supports LS2080A >> family SoCs. This patch add sbasic support for the platform. > > s/2080/2085/ > >> diff --git a/board/freescale/ls2085aqds/Makefile b/board/freescale/ls2085ardb/Makefile >> similarity index 81% >> copy from board/freescale/ls2085aqds/Makefile >> copy to board/freescale/ls2085ardb/Makefile >> index f174f33..0bfe21c 100644 >> --- a/board/freescale/ls2085aqds/Makefile >> +++ b/board/freescale/ls2085ardb/Makefile >> @@ -4,5 +4,5 @@ >> # SPDX-License-Identifier: GPL-2.0+ >> # >> >> -obj-y += ls2085aqds.o >> +obj-y += ls2085ardb.o >> obj-y += ddr.o >> diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2085ardb/README >> similarity index 73% >> copy from board/freescale/ls2085aqds/README >> copy to board/freescale/ls2085ardb/README >> index a4d7b53..19f9d2a 100644 >> --- a/board/freescale/ls2085aqds/README >> +++ b/board/freescale/ls2085ardb/README >> @@ -1,10 +1,8 @@ >> Overview >> -------- >> -The LS2080A Development System (QDS) is a high-performance computing, >> +The LS2080A Reference Design (RDB) is a high-performance computing, >> evaluation, and development platform that supports the QorIQ LS2080A >> -LayerScape Architecture processor. The LS2080AQDS provides validation and >> -SW development platform for the Freescale LS2080A processor series, with >> -a complete debugging environment. >> +LayerScape Architecture processor. > > I don't think Layerscape is supposed to be capitalized that way. > >> LS2085A SoC Overview >> ------------------ >> @@ -50,14 +48,11 @@ The LS2085A SoC includes the following function and features: >> - Service processor (SP) provides pre-boot initialization and secure-boot >> capabilities >> >> - LS2080AQDS board Overview >> + LS2080aRDB board Overview > > Inconsistent capitalization > >> #ifndef __ASSEMBLY__ >> unsigned long get_board_sys_clk(void); >> -unsigned long get_board_ddr_clk(void); >> #endif >> >> #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() >> -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() >> +#define CONFIG_DDR_CLK_FREQ 133333333 >> #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) > > Why? The timer clock source is not a fixed clock. It derives from system clock, dividing by 4. For this board, the system clock is fixed on board. But I don't think the timer clock should be hard-coded. > >> @@ -30,8 +32,8 @@ unsigned long get_board_ddr_clk(void); >> #define CONFIG_MEM_INIT_VALUE 0xdeadbeef >> #define SPD_EEPROM_ADDRESS1 0x51 >> #define SPD_EEPROM_ADDRESS2 0x52 >> -#define SPD_EEPROM_ADDRESS3 0x53 >> -#define SPD_EEPROM_ADDRESS4 0x54 >> +#define SPD_EEPROM_ADDRESS3 0x54 >> +#define SPD_EEPROM_ADDRESS4 0x53 /* Bard error */ >> #define SPD_EEPROM_ADDRESS5 0x55 >> #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ >> #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 > > I suspect this should be s/Bard/Board/ Right. > >> @@ -114,24 +106,24 @@ unsigned long get_board_ddr_clk(void); >> | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ >> | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ >> | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ >> - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ >> - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ >> - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ >> + | CSOR_NAND_PGS_4K /* Page Size = 2K */ \ >> + | CSOR_NAND_SPRZ_224 /* Spare size = 64 */ \ >> + | CSOR_NAND_PB(128)) /*Pages Per Block = 64*/ > > Comments don't match code. Result of squashing. Will fix in next version. > >> @@ -148,6 +140,7 @@ unsigned long get_board_ddr_clk(void); >> #define QIXIS_LBMAP_DFLTBANK 0x00 >> #define QIXIS_LBMAP_ALTBANK 0x04 >> #define QIXIS_RST_CTL_RESET 0x31 >> +#define QIXIS_RST_CTL_RESET_EN 0x30 >> #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 >> #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 >> #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 > > Is this really a difference between the two boards? > RDB is designed to be compatible in many ways to QDS, but it is still different. The QIXIS is compatible with most common registers, but not all of them. I will send out a new version soon. York