From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexandre Torgue Subject: Re: [PATCH v4 2/9] drivers: irqchip: Add STM32 external interrupts support Date: Thu, 8 Sep 2016 11:03:11 +0200 Message-ID: <550daf4a-0093-0b54-a305-eddd3882d993@st.com> References: <1473180341-1999-1-git-send-email-alexandre.torgue@st.com> <1473180341-1999-3-git-send-email-alexandre.torgue@st.com> <20160906173737.GU10637@io.lakedaemon.net> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20160906173737.GU10637@io.lakedaemon.net> Sender: linux-kernel-owner@vger.kernel.org To: Jason Cooper Cc: Maxime Coquelin , Thomas Gleixner , Marc Zyngier , Linus Walleij , Mark Rutland , Rob Herring , linux-gpio@vger.kernel.org, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Daniel Thompson , bruherrera@gmail.com, lee.jones@linaro.org List-Id: linux-gpio@vger.kernel.org Hi Jason, On 09/06/2016 07:37 PM, Jason Cooper wrote: > On Tue, Sep 06, 2016 at 06:45:34PM +0200, Alexandre TORGUE wrote: >> The STM32 external interrupt controller consists of edge detectors that >> generate interrupts requests or wake-up events. >> >> Each line can be independently configured as interrupt or wake-up source, >> and triggers either on rising, falling or both edges. Each line can also >> be masked independently. >> >> Signed-off-by: Maxime Coquelin >> Signed-off-by: Alexandre TORGUE >> >> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig >> index 7f87289..bc62d1f 100644 >> --- a/drivers/irqchip/Kconfig >> +++ b/drivers/irqchip/Kconfig >> @@ -264,3 +264,7 @@ config EZNPS_GIC >> select IRQ_DOMAIN >> help >> Support the EZchip NPS400 global interrupt controller >> + >> +config STM32_EXTI >> + bool >> + select IRQ_DOMAIN >> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile >> index 4c203b6..96383b2 100644 >> --- a/drivers/irqchip/Makefile >> +++ b/drivers/irqchip/Makefile >> @@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o >> obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o >> obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o >> obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o >> +obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o >> diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c >> new file mode 100644 >> index 0000000..763c17c >> --- /dev/null >> +++ b/drivers/irqchip/irq-stm32-exti.c >> @@ -0,0 +1,203 @@ >> +/* >> + * Copyright (C) Maxime Coquelin 2015 >> + * Author: Maxime Coquelin >> + * License terms: GNU General Public License (GPL), version 2 >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include > > double paste? > double paste? > > If there are no other critiques, I'll fix this up when I pull in patches > 1 and 2. > Yes bad copy/paste. I have to send a v5 with Linus (W) remarks. So I will fix it in the v5. Thanks Alex > thx, > > Jason. > >> +#include >> +#include >> +#include >> + >> +#define EXTI_IMR 0x0 >> +#define EXTI_EMR 0x4 >> +#define EXTI_RTSR 0x8 >> +#define EXTI_FTSR 0xc >> +#define EXTI_SWIER 0x10 >> +#define EXTI_PR 0x14 >> + >> +static void stm32_irq_handler(struct irq_desc *desc) >> +{ >> + struct irq_domain *domain = irq_desc_get_handler_data(desc); >> + struct irq_chip_generic *gc = domain->gc->gc[0]; >> + struct irq_chip *chip = irq_desc_get_chip(desc); >> + unsigned long pending; >> + int n; >> + >> + chained_irq_enter(chip, desc); >> + >> + while ((pending = irq_reg_readl(gc, EXTI_PR))) { >> + for_each_set_bit(n, &pending, BITS_PER_LONG) { >> + generic_handle_irq(irq_find_mapping(domain, n)); >> + irq_reg_writel(gc, BIT(n), EXTI_PR); >> + } >> + } >> + >> + chained_irq_exit(chip, desc); >> +} >> + >> +static int stm32_irq_set_type(struct irq_data *data, unsigned int type) >> +{ >> + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); >> + int pin = data->hwirq; >> + u32 rtsr, ftsr; >> + >> + irq_gc_lock(gc); >> + >> + rtsr = irq_reg_readl(gc, EXTI_RTSR); >> + ftsr = irq_reg_readl(gc, EXTI_FTSR); >> + >> + switch (type) { >> + case IRQ_TYPE_EDGE_RISING: >> + rtsr |= BIT(pin); >> + ftsr &= ~BIT(pin); >> + break; >> + case IRQ_TYPE_EDGE_FALLING: >> + rtsr &= ~BIT(pin); >> + ftsr |= BIT(pin); >> + break; >> + case IRQ_TYPE_EDGE_BOTH: >> + rtsr |= BIT(pin); >> + ftsr |= BIT(pin); >> + break; >> + default: >> + irq_gc_unlock(gc); >> + return -EINVAL; >> + } >> + >> + irq_reg_writel(gc, rtsr, EXTI_RTSR); >> + irq_reg_writel(gc, ftsr, EXTI_FTSR); >> + >> + irq_gc_unlock(gc); >> + >> + return 0; >> +} >> + >> +static int stm32_irq_set_wake(struct irq_data *data, unsigned int on) >> +{ >> + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); >> + int pin = data->hwirq; >> + u32 emr; >> + >> + irq_gc_lock(gc); >> + >> + emr = irq_reg_readl(gc, EXTI_EMR); >> + if (on) >> + emr |= BIT(pin); >> + else >> + emr &= ~BIT(pin); >> + irq_reg_writel(gc, emr, EXTI_EMR); >> + >> + irq_gc_unlock(gc); >> + >> + return 0; >> +} >> + >> +static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, >> + unsigned int nr_irqs, void *data) >> +{ >> + struct irq_chip_generic *gc = d->gc->gc[0]; >> + struct irq_fwspec *fwspec = data; >> + irq_hw_number_t hwirq; >> + >> + hwirq = fwspec->param[0]; >> + >> + irq_map_generic_chip(d, virq, hwirq); >> + irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc, >> + handle_simple_irq, NULL, NULL); >> + >> + return 0; >> +} >> + >> +static void stm32_exti_free(struct irq_domain *d, unsigned int virq, >> + unsigned int nr_irqs) >> +{ >> + struct irq_data *data = irq_get_irq_data(virq); >> + >> + irq_gc_mask_clr_bit(data->parent_data); >> + irq_domain_reset_irq_data(data); >> +} >> + >> +struct irq_domain_ops irq_exti_domain_ops = { >> + .map = irq_map_generic_chip, >> + .xlate = irq_domain_xlate_onetwocell, >> + .alloc = stm32_exti_alloc, >> + .free = stm32_exti_free, >> +}; >> + >> +static int __init stm32_exti_init(struct device_node *node, >> + struct device_node *parent) >> +{ >> + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; >> + int nr_irqs, nr_exti, ret, i; >> + struct irq_chip_generic *gc; >> + struct irq_domain *domain; >> + void *base; >> + >> + base = of_iomap(node, 0); >> + if (!base) { >> + pr_err("%s: Unable to map registers\n", node->full_name); >> + return -ENOMEM; >> + } >> + >> + /* Determine number of irqs supported */ >> + writel_relaxed(~0UL, base + EXTI_RTSR); >> + nr_exti = fls(readl_relaxed(base + EXTI_RTSR)); >> + writel_relaxed(0, base + EXTI_RTSR); >> + >> + pr_info("%s: %d External IRQs detected\n", node->full_name, nr_exti); >> + >> + domain = irq_domain_add_linear(node, nr_exti, >> + &irq_exti_domain_ops, NULL); >> + if (!domain) { >> + pr_err("%s: Could not register interrupt domain.\n", >> + node->name); >> + ret = -ENOMEM; >> + goto out_unmap; >> + } >> + >> + ret = irq_alloc_domain_generic_chips(domain, nr_exti, 1, "exti", >> + handle_edge_irq, clr, 0, 0); >> + if (ret) { >> + pr_err("%s: Could not allocate generic interrupt chip.\n", >> + node->full_name); >> + goto out_free_domain; >> + } >> + >> + gc = domain->gc->gc[0]; >> + gc->reg_base = base; >> + gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; >> + gc->chip_types->chip.name = gc->chip_types[0].chip.name; >> + gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit; >> + gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; >> + gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; >> + gc->chip_types->chip.irq_set_type = stm32_irq_set_type; >> + gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake; >> + gc->chip_types->regs.ack = EXTI_PR; >> + gc->chip_types->regs.mask = EXTI_IMR; >> + gc->chip_types->handler = handle_edge_irq; >> + >> + nr_irqs = of_irq_count(node); >> + for (i = 0; i < nr_irqs; i++) { >> + unsigned int irq = irq_of_parse_and_map(node, i); >> + >> + irq_set_handler_data(irq, domain); >> + irq_set_chained_handler(irq, stm32_irq_handler); >> + } >> + >> + return 0; >> + >> +out_free_domain: >> + irq_domain_remove(domain); >> +out_unmap: >> + iounmap(base); >> + return ret; >> +} >> + >> +IRQCHIP_DECLARE(stm32_exti, "st,stm32-exti", stm32_exti_init); >> -- >> 1.9.1 >> From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965408AbcIHJEP (ORCPT ); Thu, 8 Sep 2016 05:04:15 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:8267 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S965069AbcIHJEM (ORCPT ); Thu, 8 Sep 2016 05:04:12 -0400 Subject: Re: [PATCH v4 2/9] drivers: irqchip: Add STM32 external interrupts support To: Jason Cooper References: <1473180341-1999-1-git-send-email-alexandre.torgue@st.com> <1473180341-1999-3-git-send-email-alexandre.torgue@st.com> <20160906173737.GU10637@io.lakedaemon.net> CC: Maxime Coquelin , Thomas Gleixner , Marc Zyngier , Linus Walleij , Mark Rutland , Rob Herring , , , , , , Daniel Thompson , , From: Alexandre Torgue Message-ID: <550daf4a-0093-0b54-a305-eddd3882d993@st.com> Date: Thu, 8 Sep 2016 11:03:11 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <20160906173737.GU10637@io.lakedaemon.net> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.48.0.2] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-09-08_05:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jason, On 09/06/2016 07:37 PM, Jason Cooper wrote: > On Tue, Sep 06, 2016 at 06:45:34PM +0200, Alexandre TORGUE wrote: >> The STM32 external interrupt controller consists of edge detectors that >> generate interrupts requests or wake-up events. >> >> Each line can be independently configured as interrupt or wake-up source, >> and triggers either on rising, falling or both edges. Each line can also >> be masked independently. >> >> Signed-off-by: Maxime Coquelin >> Signed-off-by: Alexandre TORGUE >> >> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig >> index 7f87289..bc62d1f 100644 >> --- a/drivers/irqchip/Kconfig >> +++ b/drivers/irqchip/Kconfig >> @@ -264,3 +264,7 @@ config EZNPS_GIC >> select IRQ_DOMAIN >> help >> Support the EZchip NPS400 global interrupt controller >> + >> +config STM32_EXTI >> + bool >> + select IRQ_DOMAIN >> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile >> index 4c203b6..96383b2 100644 >> --- a/drivers/irqchip/Makefile >> +++ b/drivers/irqchip/Makefile >> @@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o >> obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o >> obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o >> obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o >> +obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o >> diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c >> new file mode 100644 >> index 0000000..763c17c >> --- /dev/null >> +++ b/drivers/irqchip/irq-stm32-exti.c >> @@ -0,0 +1,203 @@ >> +/* >> + * Copyright (C) Maxime Coquelin 2015 >> + * Author: Maxime Coquelin >> + * License terms: GNU General Public License (GPL), version 2 >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include > > double paste? > double paste? > > If there are no other critiques, I'll fix this up when I pull in patches > 1 and 2. > Yes bad copy/paste. I have to send a v5 with Linus (W) remarks. So I will fix it in the v5. Thanks Alex > thx, > > Jason. > >> +#include >> +#include >> +#include >> + >> +#define EXTI_IMR 0x0 >> +#define EXTI_EMR 0x4 >> +#define EXTI_RTSR 0x8 >> +#define EXTI_FTSR 0xc >> +#define EXTI_SWIER 0x10 >> +#define EXTI_PR 0x14 >> + >> +static void stm32_irq_handler(struct irq_desc *desc) >> +{ >> + struct irq_domain *domain = irq_desc_get_handler_data(desc); >> + struct irq_chip_generic *gc = domain->gc->gc[0]; >> + struct irq_chip *chip = irq_desc_get_chip(desc); >> + unsigned long pending; >> + int n; >> + >> + chained_irq_enter(chip, desc); >> + >> + while ((pending = irq_reg_readl(gc, EXTI_PR))) { >> + for_each_set_bit(n, &pending, BITS_PER_LONG) { >> + generic_handle_irq(irq_find_mapping(domain, n)); >> + irq_reg_writel(gc, BIT(n), EXTI_PR); >> + } >> + } >> + >> + chained_irq_exit(chip, desc); >> +} >> + >> +static int stm32_irq_set_type(struct irq_data *data, unsigned int type) >> +{ >> + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); >> + int pin = data->hwirq; >> + u32 rtsr, ftsr; >> + >> + irq_gc_lock(gc); >> + >> + rtsr = irq_reg_readl(gc, EXTI_RTSR); >> + ftsr = irq_reg_readl(gc, EXTI_FTSR); >> + >> + switch (type) { >> + case IRQ_TYPE_EDGE_RISING: >> + rtsr |= BIT(pin); >> + ftsr &= ~BIT(pin); >> + break; >> + case IRQ_TYPE_EDGE_FALLING: >> + rtsr &= ~BIT(pin); >> + ftsr |= BIT(pin); >> + break; >> + case IRQ_TYPE_EDGE_BOTH: >> + rtsr |= BIT(pin); >> + ftsr |= BIT(pin); >> + break; >> + default: >> + irq_gc_unlock(gc); >> + return -EINVAL; >> + } >> + >> + irq_reg_writel(gc, rtsr, EXTI_RTSR); >> + irq_reg_writel(gc, ftsr, EXTI_FTSR); >> + >> + irq_gc_unlock(gc); >> + >> + return 0; >> +} >> + >> +static int stm32_irq_set_wake(struct irq_data *data, unsigned int on) >> +{ >> + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); >> + int pin = data->hwirq; >> + u32 emr; >> + >> + irq_gc_lock(gc); >> + >> + emr = irq_reg_readl(gc, EXTI_EMR); >> + if (on) >> + emr |= BIT(pin); >> + else >> + emr &= ~BIT(pin); >> + irq_reg_writel(gc, emr, EXTI_EMR); >> + >> + irq_gc_unlock(gc); >> + >> + return 0; >> +} >> + >> +static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, >> + unsigned int nr_irqs, void *data) >> +{ >> + struct irq_chip_generic *gc = d->gc->gc[0]; >> + struct irq_fwspec *fwspec = data; >> + irq_hw_number_t hwirq; >> + >> + hwirq = fwspec->param[0]; >> + >> + irq_map_generic_chip(d, virq, hwirq); >> + irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc, >> + handle_simple_irq, NULL, NULL); >> + >> + return 0; >> +} >> + >> +static void stm32_exti_free(struct irq_domain *d, unsigned int virq, >> + unsigned int nr_irqs) >> +{ >> + struct irq_data *data = irq_get_irq_data(virq); >> + >> + irq_gc_mask_clr_bit(data->parent_data); >> + irq_domain_reset_irq_data(data); >> +} >> + >> +struct irq_domain_ops irq_exti_domain_ops = { >> + .map = irq_map_generic_chip, >> + .xlate = irq_domain_xlate_onetwocell, >> + .alloc = stm32_exti_alloc, >> + .free = stm32_exti_free, >> +}; >> + >> +static int __init stm32_exti_init(struct device_node *node, >> + struct device_node *parent) >> +{ >> + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; >> + int nr_irqs, nr_exti, ret, i; >> + struct irq_chip_generic *gc; >> + struct irq_domain *domain; >> + void *base; >> + >> + base = of_iomap(node, 0); >> + if (!base) { >> + pr_err("%s: Unable to map registers\n", node->full_name); >> + return -ENOMEM; >> + } >> + >> + /* Determine number of irqs supported */ >> + writel_relaxed(~0UL, base + EXTI_RTSR); >> + nr_exti = fls(readl_relaxed(base + EXTI_RTSR)); >> + writel_relaxed(0, base + EXTI_RTSR); >> + >> + pr_info("%s: %d External IRQs detected\n", node->full_name, nr_exti); >> + >> + domain = irq_domain_add_linear(node, nr_exti, >> + &irq_exti_domain_ops, NULL); >> + if (!domain) { >> + pr_err("%s: Could not register interrupt domain.\n", >> + node->name); >> + ret = -ENOMEM; >> + goto out_unmap; >> + } >> + >> + ret = irq_alloc_domain_generic_chips(domain, nr_exti, 1, "exti", >> + handle_edge_irq, clr, 0, 0); >> + if (ret) { >> + pr_err("%s: Could not allocate generic interrupt chip.\n", >> + node->full_name); >> + goto out_free_domain; >> + } >> + >> + gc = domain->gc->gc[0]; >> + gc->reg_base = base; >> + gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; >> + gc->chip_types->chip.name = gc->chip_types[0].chip.name; >> + gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit; >> + gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; >> + gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; >> + gc->chip_types->chip.irq_set_type = stm32_irq_set_type; >> + gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake; >> + gc->chip_types->regs.ack = EXTI_PR; >> + gc->chip_types->regs.mask = EXTI_IMR; >> + gc->chip_types->handler = handle_edge_irq; >> + >> + nr_irqs = of_irq_count(node); >> + for (i = 0; i < nr_irqs; i++) { >> + unsigned int irq = irq_of_parse_and_map(node, i); >> + >> + irq_set_handler_data(irq, domain); >> + irq_set_chained_handler(irq, stm32_irq_handler); >> + } >> + >> + return 0; >> + >> +out_free_domain: >> + irq_domain_remove(domain); >> +out_unmap: >> + iounmap(base); >> + return ret; >> +} >> + >> +IRQCHIP_DECLARE(stm32_exti, "st,stm32-exti", stm32_exti_init); >> -- >> 1.9.1 >> From mboxrd@z Thu Jan 1 00:00:00 1970 From: alexandre.torgue@st.com (Alexandre Torgue) Date: Thu, 8 Sep 2016 11:03:11 +0200 Subject: [PATCH v4 2/9] drivers: irqchip: Add STM32 external interrupts support In-Reply-To: <20160906173737.GU10637@io.lakedaemon.net> References: <1473180341-1999-1-git-send-email-alexandre.torgue@st.com> <1473180341-1999-3-git-send-email-alexandre.torgue@st.com> <20160906173737.GU10637@io.lakedaemon.net> Message-ID: <550daf4a-0093-0b54-a305-eddd3882d993@st.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Jason, On 09/06/2016 07:37 PM, Jason Cooper wrote: > On Tue, Sep 06, 2016 at 06:45:34PM +0200, Alexandre TORGUE wrote: >> The STM32 external interrupt controller consists of edge detectors that >> generate interrupts requests or wake-up events. >> >> Each line can be independently configured as interrupt or wake-up source, >> and triggers either on rising, falling or both edges. Each line can also >> be masked independently. >> >> Signed-off-by: Maxime Coquelin >> Signed-off-by: Alexandre TORGUE >> >> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig >> index 7f87289..bc62d1f 100644 >> --- a/drivers/irqchip/Kconfig >> +++ b/drivers/irqchip/Kconfig >> @@ -264,3 +264,7 @@ config EZNPS_GIC >> select IRQ_DOMAIN >> help >> Support the EZchip NPS400 global interrupt controller >> + >> +config STM32_EXTI >> + bool >> + select IRQ_DOMAIN >> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile >> index 4c203b6..96383b2 100644 >> --- a/drivers/irqchip/Makefile >> +++ b/drivers/irqchip/Makefile >> @@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o >> obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o >> obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o >> obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o >> +obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o >> diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c >> new file mode 100644 >> index 0000000..763c17c >> --- /dev/null >> +++ b/drivers/irqchip/irq-stm32-exti.c >> @@ -0,0 +1,203 @@ >> +/* >> + * Copyright (C) Maxime Coquelin 2015 >> + * Author: Maxime Coquelin >> + * License terms: GNU General Public License (GPL), version 2 >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include > > double paste? > double paste? > > If there are no other critiques, I'll fix this up when I pull in patches > 1 and 2. > Yes bad copy/paste. I have to send a v5 with Linus (W) remarks. So I will fix it in the v5. Thanks Alex > thx, > > Jason. > >> +#include >> +#include >> +#include >> + >> +#define EXTI_IMR 0x0 >> +#define EXTI_EMR 0x4 >> +#define EXTI_RTSR 0x8 >> +#define EXTI_FTSR 0xc >> +#define EXTI_SWIER 0x10 >> +#define EXTI_PR 0x14 >> + >> +static void stm32_irq_handler(struct irq_desc *desc) >> +{ >> + struct irq_domain *domain = irq_desc_get_handler_data(desc); >> + struct irq_chip_generic *gc = domain->gc->gc[0]; >> + struct irq_chip *chip = irq_desc_get_chip(desc); >> + unsigned long pending; >> + int n; >> + >> + chained_irq_enter(chip, desc); >> + >> + while ((pending = irq_reg_readl(gc, EXTI_PR))) { >> + for_each_set_bit(n, &pending, BITS_PER_LONG) { >> + generic_handle_irq(irq_find_mapping(domain, n)); >> + irq_reg_writel(gc, BIT(n), EXTI_PR); >> + } >> + } >> + >> + chained_irq_exit(chip, desc); >> +} >> + >> +static int stm32_irq_set_type(struct irq_data *data, unsigned int type) >> +{ >> + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); >> + int pin = data->hwirq; >> + u32 rtsr, ftsr; >> + >> + irq_gc_lock(gc); >> + >> + rtsr = irq_reg_readl(gc, EXTI_RTSR); >> + ftsr = irq_reg_readl(gc, EXTI_FTSR); >> + >> + switch (type) { >> + case IRQ_TYPE_EDGE_RISING: >> + rtsr |= BIT(pin); >> + ftsr &= ~BIT(pin); >> + break; >> + case IRQ_TYPE_EDGE_FALLING: >> + rtsr &= ~BIT(pin); >> + ftsr |= BIT(pin); >> + break; >> + case IRQ_TYPE_EDGE_BOTH: >> + rtsr |= BIT(pin); >> + ftsr |= BIT(pin); >> + break; >> + default: >> + irq_gc_unlock(gc); >> + return -EINVAL; >> + } >> + >> + irq_reg_writel(gc, rtsr, EXTI_RTSR); >> + irq_reg_writel(gc, ftsr, EXTI_FTSR); >> + >> + irq_gc_unlock(gc); >> + >> + return 0; >> +} >> + >> +static int stm32_irq_set_wake(struct irq_data *data, unsigned int on) >> +{ >> + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); >> + int pin = data->hwirq; >> + u32 emr; >> + >> + irq_gc_lock(gc); >> + >> + emr = irq_reg_readl(gc, EXTI_EMR); >> + if (on) >> + emr |= BIT(pin); >> + else >> + emr &= ~BIT(pin); >> + irq_reg_writel(gc, emr, EXTI_EMR); >> + >> + irq_gc_unlock(gc); >> + >> + return 0; >> +} >> + >> +static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, >> + unsigned int nr_irqs, void *data) >> +{ >> + struct irq_chip_generic *gc = d->gc->gc[0]; >> + struct irq_fwspec *fwspec = data; >> + irq_hw_number_t hwirq; >> + >> + hwirq = fwspec->param[0]; >> + >> + irq_map_generic_chip(d, virq, hwirq); >> + irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc, >> + handle_simple_irq, NULL, NULL); >> + >> + return 0; >> +} >> + >> +static void stm32_exti_free(struct irq_domain *d, unsigned int virq, >> + unsigned int nr_irqs) >> +{ >> + struct irq_data *data = irq_get_irq_data(virq); >> + >> + irq_gc_mask_clr_bit(data->parent_data); >> + irq_domain_reset_irq_data(data); >> +} >> + >> +struct irq_domain_ops irq_exti_domain_ops = { >> + .map = irq_map_generic_chip, >> + .xlate = irq_domain_xlate_onetwocell, >> + .alloc = stm32_exti_alloc, >> + .free = stm32_exti_free, >> +}; >> + >> +static int __init stm32_exti_init(struct device_node *node, >> + struct device_node *parent) >> +{ >> + unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; >> + int nr_irqs, nr_exti, ret, i; >> + struct irq_chip_generic *gc; >> + struct irq_domain *domain; >> + void *base; >> + >> + base = of_iomap(node, 0); >> + if (!base) { >> + pr_err("%s: Unable to map registers\n", node->full_name); >> + return -ENOMEM; >> + } >> + >> + /* Determine number of irqs supported */ >> + writel_relaxed(~0UL, base + EXTI_RTSR); >> + nr_exti = fls(readl_relaxed(base + EXTI_RTSR)); >> + writel_relaxed(0, base + EXTI_RTSR); >> + >> + pr_info("%s: %d External IRQs detected\n", node->full_name, nr_exti); >> + >> + domain = irq_domain_add_linear(node, nr_exti, >> + &irq_exti_domain_ops, NULL); >> + if (!domain) { >> + pr_err("%s: Could not register interrupt domain.\n", >> + node->name); >> + ret = -ENOMEM; >> + goto out_unmap; >> + } >> + >> + ret = irq_alloc_domain_generic_chips(domain, nr_exti, 1, "exti", >> + handle_edge_irq, clr, 0, 0); >> + if (ret) { >> + pr_err("%s: Could not allocate generic interrupt chip.\n", >> + node->full_name); >> + goto out_free_domain; >> + } >> + >> + gc = domain->gc->gc[0]; >> + gc->reg_base = base; >> + gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; >> + gc->chip_types->chip.name = gc->chip_types[0].chip.name; >> + gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit; >> + gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; >> + gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; >> + gc->chip_types->chip.irq_set_type = stm32_irq_set_type; >> + gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake; >> + gc->chip_types->regs.ack = EXTI_PR; >> + gc->chip_types->regs.mask = EXTI_IMR; >> + gc->chip_types->handler = handle_edge_irq; >> + >> + nr_irqs = of_irq_count(node); >> + for (i = 0; i < nr_irqs; i++) { >> + unsigned int irq = irq_of_parse_and_map(node, i); >> + >> + irq_set_handler_data(irq, domain); >> + irq_set_chained_handler(irq, stm32_irq_handler); >> + } >> + >> + return 0; >> + >> +out_free_domain: >> + irq_domain_remove(domain); >> +out_unmap: >> + iounmap(base); >> + return ret; >> +} >> + >> +IRQCHIP_DECLARE(stm32_exti, "st,stm32-exti", stm32_exti_init); >> -- >> 1.9.1 >>