From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dmitry Osipenko Subject: Re: [PATCH] drm/tegra: Reset the SOR during initialization Date: Thu, 26 Mar 2015 12:24:25 +0300 Message-ID: <5513D049.4080700@gmail.com> References: <20150324102447.GA18115@ulmo.nvidia.com> <1427273979-394-1-git-send-email-tomeu.vizoso@collabora.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <1427273979-394-1-git-send-email-tomeu.vizoso-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Tomeu Vizoso , linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: Thierry Reding , =?UTF-8?B?VGVyamUgQmVyZ3N0?= =?UTF-8?B?csO2bQ==?= , David Airlie , Stephen Warren , Alexandre Courbot , dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org 25.03.2015 11:59, Tomeu Vizoso =D0=BF=D0=B8=D1=88=D0=B5=D1=82: > As there isn't a way for the firmware on the Nyan chromebooks to hand > over the display to the kernel, and the kernel isn't redoing the whol= e > configuration at present. > > With this patch, the SOR is brought to a known state and we get corre= ct > display on every boot. > > Signed-off-by: Tomeu Vizoso > > --- > > v7: * Move the reset to the host1x_client_ops.init callback as > suggested by Thierry > * Reduced the time during which the reset line is asserted from > 20ms to 2ms > --- > drivers/gpu/drm/tegra/sor.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.= c > index 2afe478..027a25d22 100644 > --- a/drivers/gpu/drm/tegra/sor.c > +++ b/drivers/gpu/drm/tegra/sor.c > @@ -1354,12 +1354,30 @@ static int tegra_sor_init(struct host1x_clien= t *client) > } > } > > + /* > + * XXX: Remove this reset once proper hand-over from firmware to > + * kernel is possible. > + */ > + err =3D reset_control_assert(sor->rst); > + if (err < 0) { > + dev_err(sor->dev, "failed to assert SOR reset: %d\n", err); > + return err; > + } > + > err =3D clk_prepare_enable(sor->clk); > if (err < 0) { > dev_err(sor->dev, "failed to enable clock: %d\n", err); > return err; > } > > + msleep(2); > + > + err =3D reset_control_deassert(sor->rst); > + if (err < 0) { > + dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err); > + return err; > + } > + > err =3D clk_prepare_enable(sor->clk_safe); > if (err < 0) > return err; > According to kernel doc, you should use usleep_range() instead of mslee= p(). https://www.kernel.org/doc/Documentation/timers/timers-howto.txt --=20 Dmitry From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752332AbbCZJYf (ORCPT ); Thu, 26 Mar 2015 05:24:35 -0400 Received: from mail-la0-f44.google.com ([209.85.215.44]:35207 "EHLO mail-la0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752220AbbCZJY3 (ORCPT ); Thu, 26 Mar 2015 05:24:29 -0400 Message-ID: <5513D049.4080700@gmail.com> Date: Thu, 26 Mar 2015 12:24:25 +0300 From: Dmitry Osipenko User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.5.0 MIME-Version: 1.0 To: Tomeu Vizoso , linux-tegra@vger.kernel.org CC: Thierry Reding , =?UTF-8?B?VGVyamUgQmVyZ3N0?= =?UTF-8?B?csO2bQ==?= , David Airlie , Stephen Warren , Alexandre Courbot , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] drm/tegra: Reset the SOR during initialization References: <20150324102447.GA18115@ulmo.nvidia.com> <1427273979-394-1-git-send-email-tomeu.vizoso@collabora.com> In-Reply-To: <1427273979-394-1-git-send-email-tomeu.vizoso@collabora.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 25.03.2015 11:59, Tomeu Vizoso пишет: > As there isn't a way for the firmware on the Nyan chromebooks to hand > over the display to the kernel, and the kernel isn't redoing the whole > configuration at present. > > With this patch, the SOR is brought to a known state and we get correct > display on every boot. > > Signed-off-by: Tomeu Vizoso > > --- > > v7: * Move the reset to the host1x_client_ops.init callback as > suggested by Thierry > * Reduced the time during which the reset line is asserted from > 20ms to 2ms > --- > drivers/gpu/drm/tegra/sor.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c > index 2afe478..027a25d22 100644 > --- a/drivers/gpu/drm/tegra/sor.c > +++ b/drivers/gpu/drm/tegra/sor.c > @@ -1354,12 +1354,30 @@ static int tegra_sor_init(struct host1x_client *client) > } > } > > + /* > + * XXX: Remove this reset once proper hand-over from firmware to > + * kernel is possible. > + */ > + err = reset_control_assert(sor->rst); > + if (err < 0) { > + dev_err(sor->dev, "failed to assert SOR reset: %d\n", err); > + return err; > + } > + > err = clk_prepare_enable(sor->clk); > if (err < 0) { > dev_err(sor->dev, "failed to enable clock: %d\n", err); > return err; > } > > + msleep(2); > + > + err = reset_control_deassert(sor->rst); > + if (err < 0) { > + dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err); > + return err; > + } > + > err = clk_prepare_enable(sor->clk_safe); > if (err < 0) > return err; > According to kernel doc, you should use usleep_range() instead of msleep(). https://www.kernel.org/doc/Documentation/timers/timers-howto.txt -- Dmitry