From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jan Kiszka <jan.kiszka@siemens.com>
Subject: Re: x86: Question regarding the reset value of LINT0
Date: Wed, 08 Apr 2015 18:44:34 +0200
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To: Nadav Amit <nadav.amit@gmail.com>, kvm list <kvm@vger.kernel.org>
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On 2015-04-08 18:40, Nadav Amit wrote:
> Hi,
>=20
> I would appreciate if someone explains the reason for enabling LINT0 =
during
> APIC reset. This does not correspond with Intel SDM Figure 10-8: =E2=80=
=9CLocal
> Vector Table=E2=80=9D that says all LVT registers are reset to 0x1000=
0.
>=20
> In kvm_lapic_reset, I see:
>=20
> 	apic_set_reg(apic, APIC_LVT0,
> 		SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
>=20
> Which is actually pretty similar to QEMU=E2=80=99s apic_reset_common:
>=20
>     if (bsp) {
>         /*
>          * LINT0 delivery mode on CPU #0 is set to ExtInt at initiali=
zation
>          * time typically by BIOS, so PIC interrupt can be delivered =
to the
>          * processor when local APIC is enabled.
>          */
>         s->lvt[APIC_LVT_LINT0] =3D 0x700;
>     }
>=20
> Yet, in both cases, I miss the point - if it is typically done by the=
 BIOS,
> why does QEMU or KVM enable it?
>=20
> BTW: KVM seems to run fine without it, and I think setting it causes =
me
> problems in certain cases.

I suspect it has some historic BIOS backgrounds. Already tried to find
more information in the git logs of both code bases? Or something that
indicates of SeaBIOS or BochsBIOS once didn't do this initialization?

Jan

--=20
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