From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org,
Benjamin Herrenschmidt <benh@kernel.crashing.org>,
qemu-devel@nongnu.org, Alexander Graf <agraf@suse.de>
Subject: Re: [Qemu-devel] [PATCH v5 15/17] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt
Date: Tue, 25 Oct 2016 13:00:26 +0200 [thread overview]
Message-ID: <5528b94b-f36f-c071-ee85-9f6423ebaa21@kaod.org> (raw)
In-Reply-To: <20161025053007.GA11052@umbus.fritz.box>
>> +#define PSIHB_MMIO_BAR 0x00
>> +#define PSIHB_MMIO_FSPBAR 0x08
>> +#define PSIHB_MMIO_CR 0x20
>> +#define PSIHB_MMIO_SEMR 0x28
>> +#define PSIHB_MMIO_XIVR_PSI 0x30
>> +#define PSIHB_MMIO_SCR 0x40
>> +#define PSIHB_MMIO_CCR 0x48
>> +#define PSIHB_MMIO_DMA_UPADD 0x50
>> +#define PSIHB_MMIO_IRQ_STAT 0x58
>> +#define PSIHB_MMIO_XIVR_OCC 0x60
>> +#define PSIHB_MMIO_XIVR_FSI 0x68
>> +#define PSIHB_MMIO_XIVR_LPCI2C 0x70
>> +#define PSIHB_MMIO_XIVR_LOCERR 0x78
>> +#define PSIHB_MMIO_XIVR_EXT 0x80
>> +#define PSIHB_MMIO_IRSN 0x88
>> +#define PSIHB_MMIO_MAX 0x100
>> +
>> +static const uint32_t psi_mmio_to_xscom[PSIHB_MMIO_MAX / 8] = {
>
> AFAICT, this table lookup works out as:
> xscom_addr = (mmio_addr / 8) + 0xa
>
> Which makes an actual table seem like overkill.
>
>
> And in fact, since you have a /8 here, and the *8 in the xscom address
> space encoding, I suspect you could just alias the same IO region into
> both SCOM and MMIO address spaces to avoid having two dispatchers.
yes. I think this is possible. I will work on it.
Thanks,
C.
next prev parent reply other threads:[~2016-10-25 11:00 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-22 9:46 [Qemu-devel] [PATCH v5 00/17] ppc/pnv: booting the kernel and reaching user space Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 01/17] ppc: add skiboot firmware for the pnv platform Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 02/17] ppc/pnv: add skeleton PowerNV platform Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 03/17] ppc/pnv: add a PnvChip object Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 04/17] ppc/pnv: add a core mask to PnvChip Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 05/17] ppc/pnv: add a PIR handler " Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 06/17] ppc/pnv: add a PnvCore object Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 07/17] ppc/pnv: add XSCOM infrastructure Cédric Le Goater
2016-10-25 1:13 ` David Gibson
2016-10-25 6:24 ` Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 08/17] ppc/pnv: add XSCOM handlers to PnvCore Cédric Le Goater
2016-10-25 1:14 ` David Gibson
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 09/17] ppc/pnv: add a LPC controller Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 10/17] ppc/pnv: add a ISA bus Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 11/17] ppc/xics: Add "native" XICS subclass Cédric Le Goater
2016-10-25 5:08 ` David Gibson
2016-10-26 7:13 ` Cédric Le Goater
2016-10-27 3:09 ` David Gibson
2016-10-27 17:43 ` Cédric Le Goater
2016-10-28 1:00 ` David Gibson
2016-11-02 10:48 ` Cédric Le Goater
2016-11-08 1:44 ` David Gibson
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 12/17] ppc/pnv: add a XICS native to each PowerNV chip Cédric Le Goater
2016-10-24 15:42 ` Cédric Le Goater
2016-10-25 5:11 ` David Gibson
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 13/17] ppc/xics: add a xics_get_cpu_index_by_pir helper Cédric Le Goater
2016-10-25 5:36 ` David Gibson
2016-10-25 10:58 ` Cédric Le Goater
2016-10-27 3:12 ` David Gibson
2016-10-27 18:05 ` Cédric Le Goater
2016-10-28 1:03 ` David Gibson
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 14/17] ppc/xics: introduce a helper to insert a new ics Cédric Le Goater
2016-10-25 5:12 ` David Gibson
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 15/17] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt Cédric Le Goater
2016-10-25 5:30 ` David Gibson
2016-10-25 7:58 ` Cédric Le Goater
2016-10-26 0:05 ` David Gibson
2016-10-25 11:00 ` Cédric Le Goater [this message]
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 16/17] ppc/pnv: Add OCC model stub with interrupt support Cédric Le Goater
2016-10-22 9:46 ` [Qemu-devel] [PATCH v5 17/17] ppc/pnv: Add Naples chip support for LPC interrupts Cédric Le Goater
2016-10-25 5:35 ` David Gibson
2016-10-24 5:33 ` [Qemu-devel] [PATCH v5 00/17] ppc/pnv: booting the kernel and reaching user space David Gibson
2016-10-25 1:38 ` David Gibson
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