From: Deepak S <deepak.s@linux.intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2] drm/i915/chv: Implement WaDisableShadowRegForCpd
Date: Wed, 15 Apr 2015 19:09:09 +0530 [thread overview]
Message-ID: <552E69FD.60005@linux.intel.com> (raw)
In-Reply-To: <20150415111832.GA1237@intel.com>
On Wednesday 15 April 2015 04:48 PM, Ville Syrjälä wrote:
> On Wed, Apr 15, 2015 at 02:16:18PM +0530, deepak.s@linux.intel.com wrote:
>> From: Deepak S <deepak.s@linux.intel.com>
>>
>> This WA is avoid problem between shadow vs wake FIFO unload
>> problem during CPD/RC6 transactions on CHV.
>>
>> v2: Define individual bits GTFIFOCTL (Ville)
>>
>> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>> drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>> 2 files changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 9c97842..a642a58 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6206,6 +6206,8 @@ enum skl_disp_power_wells {
>> #define GTFIFOCTL 0x120008
>> #define GT_FIFO_FREE_ENTRIES_MASK 0x7f
>> #define GT_FIFO_NUM_RESERVED_ENTRIES 20
>> +#define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12)
>> +#define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11)
>>
>> #define HSW_IDICR 0x9008
>> #define IDIHASHMSK(x) (((x) & 0x3f) << 16)
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 4dd8b41..2b86915 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -6431,6 +6431,11 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
>> /* WaDisableSDEUnitClockGating:chv */
>> I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>> GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>> +
>> + /* WaDisableShadowRegForCpd */
>> + I915_WRITE(GTFIFOCTL, I915_READ(GTFIFOCTL) |
>> + GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
>> + GT_FIFO_CTL_RC6_POLICY_STALL);
> uncore early sanitize would still seem like the better place for this.
you mean intel_uncore_early_sanitize(). But func is called during early resume right?
Since GTFIFOCTL will be saved and resorted by gunit. I think programming reg in
cherryview_init_clock_gating should be good enough?
>> }
>>
>> static void g4x_init_clock_gating(struct drm_device *dev)
>> --
>> 1.9.1
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next prev parent reply other threads:[~2015-04-15 13:42 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-14 10:28 [PATCH] drm/i915/chv: Implement WaDisableShadowRegForCpd deepak.s
2015-04-14 10:59 ` Ville Syrjälä
2015-04-15 8:02 ` Deepak S
2015-04-15 8:46 ` [PATCH v2] " deepak.s
2015-04-15 11:18 ` Ville Syrjälä
2015-04-15 13:39 ` Deepak S [this message]
2015-04-15 14:11 ` [PATCH v3] " deepak.s
2015-04-15 18:39 ` Ville Syrjälä
2015-04-16 3:19 ` Deepak S
2015-04-16 3:21 ` [PATCH v4] " deepak.s
2015-04-16 21:05 ` shuang.he
2015-04-28 14:41 ` Jani Nikula
2015-04-16 2:36 ` [PATCH v3] " shuang.he
2015-04-15 18:19 ` [PATCH v2] " shuang.he
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