From mboxrd@z Thu Jan  1 00:00:00 1970
From: Nikolay Dimitrov <picmaster@mail.bg>
Date: Mon, 18 May 2015 00:37:37 +0300
Subject: [U-Boot] [PATCH v2 1/2] imx: mx6: add get_cpu_speed_grade_hz
 func to return MHz speed grade from OTP
In-Reply-To: <1431580121-24726-2-git-send-email-tharvey@gateworks.com>
References: <1431580121-24726-1-git-send-email-tharvey@gateworks.com>
 <1431580121-24726-2-git-send-email-tharvey@gateworks.com>
Message-ID: <55590A21.1070805@mail.bg>
List-Id: <u-boot.lists.denx.de>
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To: u-boot@lists.denx.de

Hi Tim,

On 05/14/2015 08:08 AM, Tim Harvey wrote:
> The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING
> indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description
> Table. Return this frequency so that it can be used elsewhere.
>
> Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
> their Fusemap Description Table however Freescale has confirmed that these
> eFUSE bits match the description within the IMX6DQRM and that they will
> be added to the next revision of the respective reference manuals.
>
> These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades.
>
> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
> ---
>   arch/arm/cpu/armv7/mx6/soc.c              | 41 +++++++++++++++++++++++++++++++
>   arch/arm/include/asm/arch-mx6/sys_proto.h |  1 +
>   2 files changed, 42 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index dd34138..71fa1fb 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -83,6 +83,47 @@ u32 get_cpu_rev(void)
>   	return (type << 12) | (reg + 0x10);
>   }
>
> +/*
> + * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
> + * defines a 2-bit SPEED_GRADING
> + */
> +#define OCOTP_CFG3_SPEED_SHIFT	16
> +#define OCOTP_CFG3_SPEED_800MHZ	0
> +#define OCOTP_CFG3_SPEED_850MHZ	1
> +#define OCOTP_CFG3_SPEED_1GHZ	2
> +#define OCOTP_CFG3_SPEED_1P2GHZ	3
> +
> +u32 get_cpu_speed_grade_hz(void)
> +{
> +	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
> +	struct fuse_bank *bank = &ocotp->bank[0];
> +	struct fuse_bank0_regs *fuse =
> +		(struct fuse_bank0_regs *)bank->fuse_regs;
> +	uint32_t val;
> +
> +	val = readl(&fuse->cfg3);
> +	val >>= OCOTP_CFG3_SPEED_SHIFT;
> +	val &= 0x3;
> +
> +	switch (val) {
> +	/* Valid for IMX6DQ */
> +	case OCOTP_CFG3_SPEED_1P2GHZ:
> +		if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
> +			return 1200000000;
> +	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
> +	case OCOTP_CFG3_SPEED_1GHZ:
> +		return 996000000;
> +	/* Valid for IMX6DQ */
> +	case OCOTP_CFG3_SPEED_850MHZ:
> +		if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
> +			return 852000000;
> +	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
> +	case OCOTP_CFG3_SPEED_800MHZ:
> +		return 792000000;
> +	}
> +	return 0;
> +}
> +
>   #ifdef CONFIG_REVISION_TAG
>   u32 __weak get_board_rev(void)
>   {
> diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
> index 28ba844..a2cd0a9 100644
> --- a/arch/arm/include/asm/arch-mx6/sys_proto.h
> +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
> @@ -16,6 +16,7 @@
>
>   u32 get_nr_cpus(void);
>   u32 get_cpu_rev(void);
> +u32 get_cpu_speed_grade_hz(void);
>
>   /* returns MXC_CPU_ value */
>   #define cpu_type(rev) (((rev) >> 12)&0xff)
>


U-Boot 2015.07-rc1-21804-gaf1db4a-dirty (May 18 2015 - 00:31:26)

CPU:   Freescale i.MX6SOLO rev1.1 996 MHz (running at 792 MHz)
Reset cause: WDOG
Board: RIoTboard


Tested-by: Nikolay Dimitrov <picmaster@mail.bg>

Regards,
Nikolay