From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757558AbbE3JVV (ORCPT ); Sat, 30 May 2015 05:21:21 -0400 Received: from mail-wi0-f176.google.com ([209.85.212.176]:34043 "EHLO mail-wi0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757589AbbE3JVL (ORCPT ); Sat, 30 May 2015 05:21:11 -0400 Message-ID: <55698104.2070205@gmail.com> Date: Sat, 30 May 2015 11:21:08 +0200 From: Maxime Coquelin User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Daniel Thompson , Mike Turquette , Stephen Boyd CC: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Kamil Lulko , Andreas Farber , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, patches@linaro.org, linaro-kernel@lists.linaro.org Subject: Re: [PATCH v2 2/4] dt-bindings: Document the STM32F4 clock bindings References: <1432327273-6810-1-git-send-email-daniel.thompson@linaro.org> <1432972448-10332-1-git-send-email-daniel.thompson@linaro.org> <1432972448-10332-3-git-send-email-daniel.thompson@linaro.org> In-Reply-To: <1432972448-10332-3-git-send-email-daniel.thompson@linaro.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org HI Daniel, On 05/30/2015 09:54 AM, Daniel Thompson wrote: > This adds documentation of device tree bindings for the clock related > portions of the STM32 RCC block. > > Signed-off-by: Daniel Thompson > --- > .../devicetree/bindings/clock/st,stm32-rcc.txt | 65 ++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt > > diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt > new file mode 100644 > index 0000000..9715d09 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt > @@ -0,0 +1,65 @@ > +STMicroelectronics STM32 Reset and Clock Controller > +=================================================== > + > +The RCC IP is both a reset and a clock controller. This documentation only > +describes the clock part. > + > +Please also refer to clock-bindings.txt in this directory for common clock > +controller binding usage. > + > +Required properties: > +- compatible: Should be "st,stm32f42xx-rcc" > +- reg: should be register base and length as documented in the > + datasheet > +- #clock-cells: 2, device nodes should specify the clock in their "clocks" > + property, containing a phandle to the clock device node, an index selecting > + between gated clocks and other clocks and an index specifying the clock to > + use. > + > +Example: > + > + rcc: rcc@40023800 { > + #clock-cells = <2> > + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; > + reg = <0x40023800 0x400>; > + }; > + > +Specifying gated clocks > +======================= > + > +The primary index must be set to 0. > + > +The secondary index is the bit number within the RCC register bank, starting > +from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). > + > +It is calculated as: index = register_offset / 4 * 32 + bit_offset. > +Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31). > + > +Example: > + > + /* Gated clock, AHB1 bit 0 (GPIOA) */ > + ... { > + clocks = <&rcc 0 0> > + }; > + > + /* Gated clock, AHB2 bit 4 (GPIOA) */ s/GPIOA/CRYP/ > + ... { > + clocks = <&rcc 0 36> > + }; > + > +Specifying other clocks > +======================= > + > +The primary index must be set to 1. > + > +The secondary index is bound with the following magic numbers: > + > + 0 SYSTICK > + 1 FCLK How do you plan to handle the SAI & I2S clocks? By adding index 3? From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Coquelin Subject: Re: [PATCH v2 2/4] dt-bindings: Document the STM32F4 clock bindings Date: Sat, 30 May 2015 11:21:08 +0200 Message-ID: <55698104.2070205@gmail.com> References: <1432327273-6810-1-git-send-email-daniel.thompson@linaro.org> <1432972448-10332-1-git-send-email-daniel.thompson@linaro.org> <1432972448-10332-3-git-send-email-daniel.thompson@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1432972448-10332-3-git-send-email-daniel.thompson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Daniel Thompson , Mike Turquette , Stephen Boyd Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Kamil Lulko , Andreas Farber , linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, patches-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, linaro-kernel-cunTk1MwBs8s++Sfvej+rw@public.gmane.org List-Id: devicetree@vger.kernel.org HI Daniel, On 05/30/2015 09:54 AM, Daniel Thompson wrote: > This adds documentation of device tree bindings for the clock related > portions of the STM32 RCC block. > > Signed-off-by: Daniel Thompson > --- > .../devicetree/bindings/clock/st,stm32-rcc.txt | 65 ++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt > > diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt > new file mode 100644 > index 0000000..9715d09 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt > @@ -0,0 +1,65 @@ > +STMicroelectronics STM32 Reset and Clock Controller > +=================================================== > + > +The RCC IP is both a reset and a clock controller. This documentation only > +describes the clock part. > + > +Please also refer to clock-bindings.txt in this directory for common clock > +controller binding usage. > + > +Required properties: > +- compatible: Should be "st,stm32f42xx-rcc" > +- reg: should be register base and length as documented in the > + datasheet > +- #clock-cells: 2, device nodes should specify the clock in their "clocks" > + property, containing a phandle to the clock device node, an index selecting > + between gated clocks and other clocks and an index specifying the clock to > + use. > + > +Example: > + > + rcc: rcc@40023800 { > + #clock-cells = <2> > + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; > + reg = <0x40023800 0x400>; > + }; > + > +Specifying gated clocks > +======================= > + > +The primary index must be set to 0. > + > +The secondary index is the bit number within the RCC register bank, starting > +from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). > + > +It is calculated as: index = register_offset / 4 * 32 + bit_offset. > +Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31). > + > +Example: > + > + /* Gated clock, AHB1 bit 0 (GPIOA) */ > + ... { > + clocks = <&rcc 0 0> > + }; > + > + /* Gated clock, AHB2 bit 4 (GPIOA) */ s/GPIOA/CRYP/ > + ... { > + clocks = <&rcc 0 36> > + }; > + > +Specifying other clocks > +======================= > + > +The primary index must be set to 1. > + > +The secondary index is bound with the following magic numbers: > + > + 0 SYSTICK > + 1 FCLK How do you plan to handle the SAI & I2S clocks? By adding index 3? -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: mcoquelin.stm32@gmail.com (Maxime Coquelin) Date: Sat, 30 May 2015 11:21:08 +0200 Subject: [PATCH v2 2/4] dt-bindings: Document the STM32F4 clock bindings In-Reply-To: <1432972448-10332-3-git-send-email-daniel.thompson@linaro.org> References: <1432327273-6810-1-git-send-email-daniel.thompson@linaro.org> <1432972448-10332-1-git-send-email-daniel.thompson@linaro.org> <1432972448-10332-3-git-send-email-daniel.thompson@linaro.org> Message-ID: <55698104.2070205@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org HI Daniel, On 05/30/2015 09:54 AM, Daniel Thompson wrote: > This adds documentation of device tree bindings for the clock related > portions of the STM32 RCC block. > > Signed-off-by: Daniel Thompson > --- > .../devicetree/bindings/clock/st,stm32-rcc.txt | 65 ++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/st,stm32-rcc.txt > > diff --git a/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt > new file mode 100644 > index 0000000..9715d09 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/st,stm32-rcc.txt > @@ -0,0 +1,65 @@ > +STMicroelectronics STM32 Reset and Clock Controller > +=================================================== > + > +The RCC IP is both a reset and a clock controller. This documentation only > +describes the clock part. > + > +Please also refer to clock-bindings.txt in this directory for common clock > +controller binding usage. > + > +Required properties: > +- compatible: Should be "st,stm32f42xx-rcc" > +- reg: should be register base and length as documented in the > + datasheet > +- #clock-cells: 2, device nodes should specify the clock in their "clocks" > + property, containing a phandle to the clock device node, an index selecting > + between gated clocks and other clocks and an index specifying the clock to > + use. > + > +Example: > + > + rcc: rcc at 40023800 { > + #clock-cells = <2> > + compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; > + reg = <0x40023800 0x400>; > + }; > + > +Specifying gated clocks > +======================= > + > +The primary index must be set to 0. > + > +The secondary index is the bit number within the RCC register bank, starting > +from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30). > + > +It is calculated as: index = register_offset / 4 * 32 + bit_offset. > +Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31). > + > +Example: > + > + /* Gated clock, AHB1 bit 0 (GPIOA) */ > + ... { > + clocks = <&rcc 0 0> > + }; > + > + /* Gated clock, AHB2 bit 4 (GPIOA) */ s/GPIOA/CRYP/ > + ... { > + clocks = <&rcc 0 36> > + }; > + > +Specifying other clocks > +======================= > + > +The primary index must be set to 1. > + > +The secondary index is bound with the following magic numbers: > + > + 0 SYSTICK > + 1 FCLK How do you plan to handle the SAI & I2S clocks? By adding index 3?