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Date: Mon, 01 Jun 2015 15:56:54 +0200
From: Philippe Bergheaud <felix@linux.vnet.ibm.com>
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To: Michael Neuling <mikey@neuling.org>
CC: imunsie@au1.ibm.com, linuxppc-dev@ozlabs.org, vaibhav@linux.vnet.ibm.com
Subject: Re: [PATCH] cxl: Set up and enable PSL Timebase
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Michael Neuling wrote:
 > Please use negative error codes here.  -EIO?
 > And check it here.

Mikey,

I am reluctant to fail the entire CAPI init after a PSL timebase sync failure.
If we ignore the error, the CAPI device stays available (without timebase sync).
If we honour the error, the CAPI device fails entirely.

I know three reasons why PSL timebase sync can fail:
1. h/w failure
2. OPAL did not initialize the CAPP timebase (wrong OPAL version)
3. the PCIe bus was not powered off/on between shutdown and reboot

I think that it is premature to choose to fail the entire CAPI init in all cases.
In particular, point 3. introduces a regression, as PCIe off/on was never a requirement for booting CAPI on P8.

I have tried one workaround do far: forcing the 0 to 1 transition of the tb bit of the PSL register TB_CTLSTAT.
In vain.

What do you think?

Philippe