Hi Leonid, On 02/06/15 01:09, Leonid Yegoshin wrote:CPUs may occasionally have problems in accordance with HW team."have problems in accordance with HW team" is a bit confusing. What do you mean?
yes, it is possible for the stores to be observed out of order The SC B can complete if it has ownership and the SW A is still waiting for ownership. This scenario was also possible on older cores. (snip) -----Original Message----- From: Leonid Yegoshin Subject: more SYNC issues ... I want to know - do XXXX orders stores without SYNC? Let's consider a scenario: SW $0, A (cache miss) ... LL $1, B (cache hit) .. SC $1, B (cache hit again) B (is not taken!) .. SYNC 0x10 Is it possible for other core to get new value of B before new value of A between SC-B and SYNC? -------------------------------------------------------------Another mail, another processor:
Hi Leonid
LL
(cacheable)
Miss
LW
(cacheable)
Miss, different cacheline
Actually *true*? P5600 you mean? Same in Kconfig help text.
It feels wrong to be giving the user this option. Can't we just select WEAK_REORDERING_BEYOND_LLSC automatically based on the hardware that needs to be supported by the kernel configuration (e.g. CPU_MIPSR6 or CPU_MIPS32_R2)?
Those who care about mips r2 performance on hardware which doesn't strictly need it can always speak up / add an exception. Out of interest, are futex operations safe with weak llsc ordering, on the premise that they're mainly used by userland so ordering with normal kernel accesses just doesn't matter in practice?
This patch does 3 logically separable things: 1) add smp_release/smp_acquire based on MIPS_LIGHTWEIGHT_SYNC and weaken smp_store_release()/smp_load_acquire() to use them. 2) weaken llsc barriers when MIPS_LIGHTWEIGHT_SYNC. 3) the MIPS_ENFORCE_WEAK_REORDERING_BEYOND_LLSC Kconfig stuff (or whatever method to select WEAK_REORDERING_BEYOND_LLSC more often). Any reason not to split them, and give a clear description of each?