From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40746) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0qLV-00018Y-Fe for qemu-devel@nongnu.org; Fri, 05 Jun 2015 08:03:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0qLP-0004uy-S4 for qemu-devel@nongnu.org; Fri, 05 Jun 2015 08:03:33 -0400 Received: from mail.emea.novell.com ([130.57.118.101]:55425) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0qLP-0004ui-G9 for qemu-devel@nongnu.org; Fri, 05 Jun 2015 08:03:27 -0400 Message-Id: <5571AC2E020000780008156B@mail.emea.novell.com> Date: Fri, 05 Jun 2015 13:03:26 +0100 From: "Jan Beulich" References: <5571AA3B020000780008152E@mail.emea.novell.com> In-Reply-To: <5571AA3B020000780008152E@mail.emea.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__PartC2F6EB1E.2__=" Subject: [Qemu-devel] [PATCH 4/6] xen/pass-through: correctly deal with RW1C bits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: xen-devel , Stefano Stabellini This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__PartC2F6EB1E.2__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Introduce yet another mask for them, so that the generic routine can handle them, at once rendering xen_pt_pmcsr_reg_write() superfluous. Signed-off-by: Jan Beulich --- a/qemu/upstream/hw/xen/xen_pt.h +++ b/qemu/upstream/hw/xen/xen_pt.h @@ -105,6 +105,8 @@ struct XenPTRegInfo { uint32_t res_mask; /* reg read only field mask (ON:RO/ROS, OFF:other) */ uint32_t ro_mask; + /* reg read/write-1-clear field mask (ON:RW1C/RW1CS, OFF:other) */ + uint32_t rw1c_mask; /* reg emulate field mask (ON:emu, OFF:passthrough) */ uint32_t emu_mask; xen_pt_conf_reg_init init; --- a/qemu/upstream/hw/xen/xen_pt_config_init.c +++ b/qemu/upstream/hw/xen/xen_pt_config_init.c @@ -176,7 +176,8 @@ static int xen_pt_byte_reg_write(XenPCIP cfg_entry->data =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, = writable_mask); =20 /* create value for writing to I/O device register */ - *val =3D XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); + *val =3D XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask, + throughable_mask); =20 return 0; } @@ -193,7 +194,8 @@ static int xen_pt_word_reg_write(XenPCIP cfg_entry->data =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, = writable_mask); =20 /* create value for writing to I/O device register */ - *val =3D XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); + *val =3D XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask, + throughable_mask); =20 return 0; } @@ -210,7 +212,8 @@ static int xen_pt_long_reg_write(XenPCIP cfg_entry->data =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, = writable_mask); =20 /* create value for writing to I/O device register */ - *val =3D XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); + *val =3D XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask, + throughable_mask); =20 return 0; } @@ -611,6 +614,7 @@ static XenPTRegInfo xen_pt_emu_reg_heade .init_val =3D 0x0000, .res_mask =3D 0x0007, .ro_mask =3D 0x06F8, + .rw1c_mask =3D 0xF900, .emu_mask =3D 0x0010, .init =3D xen_pt_status_reg_init, .u.w.read =3D xen_pt_word_reg_read, @@ -910,6 +914,7 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[ .size =3D 2, .res_mask =3D 0xFFC0, .ro_mask =3D 0x0030, + .rw1c_mask =3D 0x000F, .init =3D xen_pt_common_reg_init, .u.w.read =3D xen_pt_word_reg_read, .u.w.write =3D xen_pt_word_reg_write, @@ -930,6 +935,7 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[ .offset =3D PCI_EXP_LNKSTA, .size =3D 2, .ro_mask =3D 0x3FFF, + .rw1c_mask =3D 0xC000, .init =3D xen_pt_common_reg_init, .u.w.read =3D xen_pt_word_reg_read, .u.w.write =3D xen_pt_word_reg_write, @@ -966,26 +972,6 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[ * Power Management Capability */ =20 -/* write Power Management Control/Status register */ -static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState *s, - XenPTReg *cfg_entry, uint16_t *val, - uint16_t dev_value, uint16_t valid_mask)= -{ - XenPTRegInfo *reg =3D cfg_entry->reg; - uint16_t writable_mask =3D 0; - uint16_t throughable_mask =3D get_throughable_mask(s, reg, valid_mask)= ; - - /* modify emulate register */ - writable_mask =3D reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, = writable_mask); - - /* create value for writing to I/O device register */ - *val =3D XEN_PT_MERGE_VALUE(*val, dev_value & ~PCI_PM_CTRL_PME_STATUS,= - throughable_mask); - - return 0; -} - /* Power Management Capability reg static information table */ static XenPTRegInfo xen_pt_emu_reg_pm[] =3D { /* Next Pointer reg */ @@ -1016,11 +1002,12 @@ static XenPTRegInfo xen_pt_emu_reg_pm[]=20 .size =3D 2, .init_val =3D 0x0008, .res_mask =3D 0x00F0, - .ro_mask =3D 0xE10C, + .ro_mask =3D 0x610C, + .rw1c_mask =3D 0x8000, .emu_mask =3D 0x810B, .init =3D xen_pt_common_reg_init, .u.w.read =3D xen_pt_word_reg_read, - .u.w.write =3D xen_pt_pmcsr_reg_write, + .u.w.write =3D xen_pt_word_reg_write, }, { .size =3D 0, --=__PartC2F6EB1E.2__= Content-Type: text/plain; name="qemu-pt-RW1C-bits.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="qemu-pt-RW1C-bits.patch" xen/pass-through: correctly deal with RW1C bits=0A=0AIntroduce yet another = mask for them, so that the generic routine can=0Ahandle them, at once = rendering xen_pt_pmcsr_reg_write() superfluous.=0A=0ASigned-off-by: Jan = Beulich =0A=0A--- a/qemu/upstream/hw/xen/xen_pt.h=0A+++ = b/qemu/upstream/hw/xen/xen_pt.h=0A@@ -105,6 +105,8 @@ struct XenPTRegInfo = {=0A uint32_t res_mask;=0A /* reg read only field mask (ON:RO/ROS, = OFF:other) */=0A uint32_t ro_mask;=0A+ /* reg read/write-1-clear = field mask (ON:RW1C/RW1CS, OFF:other) */=0A+ uint32_t rw1c_mask;=0A = /* reg emulate field mask (ON:emu, OFF:passthrough) */=0A uint32_t = emu_mask;=0A xen_pt_conf_reg_init init;=0A--- a/qemu/upstream/hw/xen/xe= n_pt_config_init.c=0A+++ b/qemu/upstream/hw/xen/xen_pt_config_init.c=0A@@ = -176,7 +176,8 @@ static int xen_pt_byte_reg_write(XenPCIP=0A cfg_entry-= >data =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);=0A =0A = /* create value for writing to I/O device register */=0A- *val =3D = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);=0A+ *val =3D = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask,=0A+ = throughable_mask);=0A =0A return 0;=0A }=0A@@ -193,7 = +194,8 @@ static int xen_pt_word_reg_write(XenPCIP=0A cfg_entry->data = =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);=0A =0A = /* create value for writing to I/O device register */=0A- *val =3D = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);=0A+ *val =3D = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask,=0A+ = throughable_mask);=0A =0A return 0;=0A }=0A@@ -210,7 = +212,8 @@ static int xen_pt_long_reg_write(XenPCIP=0A cfg_entry->data = =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);=0A =0A = /* create value for writing to I/O device register */=0A- *val =3D = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);=0A+ *val =3D = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask,=0A+ = throughable_mask);=0A =0A return 0;=0A }=0A@@ -611,6 = +614,7 @@ static XenPTRegInfo xen_pt_emu_reg_heade=0A .init_val = =3D 0x0000,=0A .res_mask =3D 0x0007,=0A .ro_mask =3D = 0x06F8,=0A+ .rw1c_mask =3D 0xF900,=0A .emu_mask =3D = 0x0010,=0A .init =3D xen_pt_status_reg_init,=0A = .u.w.read =3D xen_pt_word_reg_read,=0A@@ -910,6 +914,7 @@ static = XenPTRegInfo xen_pt_emu_reg_pcie[=0A .size =3D 2,=0A = .res_mask =3D 0xFFC0,=0A .ro_mask =3D 0x0030,=0A+ = .rw1c_mask =3D 0x000F,=0A .init =3D xen_pt_common_reg_init,= =0A .u.w.read =3D xen_pt_word_reg_read,=0A .u.w.write = =3D xen_pt_word_reg_write,=0A@@ -930,6 +935,7 @@ static XenPTRegInfo = xen_pt_emu_reg_pcie[=0A .offset =3D PCI_EXP_LNKSTA,=0A = .size =3D 2,=0A .ro_mask =3D 0x3FFF,=0A+ .rw1c_mask= =3D 0xC000,=0A .init =3D xen_pt_common_reg_init,=0A = .u.w.read =3D xen_pt_word_reg_read,=0A .u.w.write =3D = xen_pt_word_reg_write,=0A@@ -966,26 +972,6 @@ static XenPTRegInfo = xen_pt_emu_reg_pcie[=0A * Power Management Capability=0A */=0A =0A-/* = write Power Management Control/Status register */=0A-static int xen_pt_pmcs= r_reg_write(XenPCIPassthroughState *s,=0A- = XenPTReg *cfg_entry, uint16_t *val,=0A- = uint16_t dev_value, uint16_t valid_mask)=0A-{=0A- XenPTRegInfo *reg =3D = cfg_entry->reg;=0A- uint16_t writable_mask =3D 0;=0A- uint16_t = throughable_mask =3D get_throughable_mask(s, reg, valid_mask);=0A-=0A- = /* modify emulate register */=0A- writable_mask =3D reg->emu_mask & = ~reg->ro_mask & valid_mask;=0A- cfg_entry->data =3D XEN_PT_MERGE_VALUE(*= val, cfg_entry->data, writable_mask);=0A-=0A- /* create value for = writing to I/O device register */=0A- *val =3D XEN_PT_MERGE_VALUE(*val, = dev_value & ~PCI_PM_CTRL_PME_STATUS,=0A- = throughable_mask);=0A-=0A- return 0;=0A-}=0A-=0A /* Power Management = Capability reg static information table */=0A static XenPTRegInfo = xen_pt_emu_reg_pm[] =3D {=0A /* Next Pointer reg */=0A@@ -1016,11 = +1002,12 @@ static XenPTRegInfo xen_pt_emu_reg_pm[] =0A .size = =3D 2,=0A .init_val =3D 0x0008,=0A .res_mask =3D = 0x00F0,=0A- .ro_mask =3D 0xE10C,=0A+ .ro_mask =3D = 0x610C,=0A+ .rw1c_mask =3D 0x8000,=0A .emu_mask =3D = 0x810B,=0A .init =3D xen_pt_common_reg_init,=0A = .u.w.read =3D xen_pt_word_reg_read,=0A- .u.w.write =3D xen_pt_pmc= sr_reg_write,=0A+ .u.w.write =3D xen_pt_word_reg_write,=0A = },=0A {=0A .size =3D 0,=0A --=__PartC2F6EB1E.2__=-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH 4/6] xen/pass-through: correctly deal with RW1C bits Date: Fri, 05 Jun 2015 13:03:26 +0100 Message-ID: <5571AC2E020000780008156B@mail.emea.novell.com> References: <5571AA3B020000780008152E@mail.emea.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__PartC2F6EB1E.1__=" Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1Z0qLQ-0008Ut-H2 for xen-devel@lists.xenproject.org; Fri, 05 Jun 2015 12:03:28 +0000 In-Reply-To: <5571AA3B020000780008152E@mail.emea.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: qemu-devel@nongnu.org Cc: xen-devel , Stefano Stabellini List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__PartC2F6EB1E.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Introduce yet another mask for them, so that the generic routine can handle them, at once rendering xen_pt_pmcsr_reg_write() superfluous. Signed-off-by: Jan Beulich --- a/qemu/upstream/hw/xen/xen_pt.h +++ b/qemu/upstream/hw/xen/xen_pt.h @@ -105,6 +105,8 @@ struct XenPTRegInfo { uint32_t res_mask; /* reg read only field mask (ON:RO/ROS, OFF:other) */ uint32_t ro_mask; + /* reg read/write-1-clear field mask (ON:RW1C/RW1CS, OFF:other) */ + uint32_t rw1c_mask; /* reg emulate field mask (ON:emu, OFF:passthrough) */ uint32_t emu_mask; xen_pt_conf_reg_init init; --- a/qemu/upstream/hw/xen/xen_pt_config_init.c +++ b/qemu/upstream/hw/xen/xen_pt_config_init.c @@ -176,7 +176,8 @@ static int xen_pt_byte_reg_write(XenPCIP cfg_entry->data =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, = writable_mask); =20 /* create value for writing to I/O device register */ - *val =3D XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); + *val =3D XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask, + throughable_mask); =20 return 0; } @@ -193,7 +194,8 @@ static int xen_pt_word_reg_write(XenPCIP cfg_entry->data =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, = writable_mask); =20 /* create value for writing to I/O device register */ - *val =3D XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); + *val =3D XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask, + throughable_mask); =20 return 0; } @@ -210,7 +212,8 @@ static int xen_pt_long_reg_write(XenPCIP cfg_entry->data =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, = writable_mask); =20 /* create value for writing to I/O device register */ - *val =3D XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); + *val =3D XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask, + throughable_mask); =20 return 0; } @@ -611,6 +614,7 @@ static XenPTRegInfo xen_pt_emu_reg_heade .init_val =3D 0x0000, .res_mask =3D 0x0007, .ro_mask =3D 0x06F8, + .rw1c_mask =3D 0xF900, .emu_mask =3D 0x0010, .init =3D xen_pt_status_reg_init, .u.w.read =3D xen_pt_word_reg_read, @@ -910,6 +914,7 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[ .size =3D 2, .res_mask =3D 0xFFC0, .ro_mask =3D 0x0030, + .rw1c_mask =3D 0x000F, .init =3D xen_pt_common_reg_init, .u.w.read =3D xen_pt_word_reg_read, .u.w.write =3D xen_pt_word_reg_write, @@ -930,6 +935,7 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[ .offset =3D PCI_EXP_LNKSTA, .size =3D 2, .ro_mask =3D 0x3FFF, + .rw1c_mask =3D 0xC000, .init =3D xen_pt_common_reg_init, .u.w.read =3D xen_pt_word_reg_read, .u.w.write =3D xen_pt_word_reg_write, @@ -966,26 +972,6 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[ * Power Management Capability */ =20 -/* write Power Management Control/Status register */ -static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState *s, - XenPTReg *cfg_entry, uint16_t *val, - uint16_t dev_value, uint16_t valid_mask)= -{ - XenPTRegInfo *reg =3D cfg_entry->reg; - uint16_t writable_mask =3D 0; - uint16_t throughable_mask =3D get_throughable_mask(s, reg, valid_mask)= ; - - /* modify emulate register */ - writable_mask =3D reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, = writable_mask); - - /* create value for writing to I/O device register */ - *val =3D XEN_PT_MERGE_VALUE(*val, dev_value & ~PCI_PM_CTRL_PME_STATUS,= - throughable_mask); - - return 0; -} - /* Power Management Capability reg static information table */ static XenPTRegInfo xen_pt_emu_reg_pm[] =3D { /* Next Pointer reg */ @@ -1016,11 +1002,12 @@ static XenPTRegInfo xen_pt_emu_reg_pm[]=20 .size =3D 2, .init_val =3D 0x0008, .res_mask =3D 0x00F0, - .ro_mask =3D 0xE10C, + .ro_mask =3D 0x610C, + .rw1c_mask =3D 0x8000, .emu_mask =3D 0x810B, .init =3D xen_pt_common_reg_init, .u.w.read =3D xen_pt_word_reg_read, - .u.w.write =3D xen_pt_pmcsr_reg_write, + .u.w.write =3D xen_pt_word_reg_write, }, { .size =3D 0, --=__PartC2F6EB1E.1__= Content-Type: text/plain; name="qemu-pt-RW1C-bits.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="qemu-pt-RW1C-bits.patch" xen/pass-through: correctly deal with RW1C bits=0A=0AIntroduce yet another = mask for them, so that the generic routine can=0Ahandle them, at once = rendering xen_pt_pmcsr_reg_write() superfluous.=0A=0ASigned-off-by: Jan = Beulich =0A=0A--- a/qemu/upstream/hw/xen/xen_pt.h=0A+++ = b/qemu/upstream/hw/xen/xen_pt.h=0A@@ -105,6 +105,8 @@ struct XenPTRegInfo = {=0A uint32_t res_mask;=0A /* reg read only field mask (ON:RO/ROS, = OFF:other) */=0A uint32_t ro_mask;=0A+ /* reg read/write-1-clear = field mask (ON:RW1C/RW1CS, OFF:other) */=0A+ uint32_t rw1c_mask;=0A = /* reg emulate field mask (ON:emu, OFF:passthrough) */=0A uint32_t = emu_mask;=0A xen_pt_conf_reg_init init;=0A--- a/qemu/upstream/hw/xen/xe= n_pt_config_init.c=0A+++ b/qemu/upstream/hw/xen/xen_pt_config_init.c=0A@@ = -176,7 +176,8 @@ static int xen_pt_byte_reg_write(XenPCIP=0A cfg_entry-= >data =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);=0A =0A = /* create value for writing to I/O device register */=0A- *val =3D = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);=0A+ *val =3D = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask,=0A+ = throughable_mask);=0A =0A return 0;=0A }=0A@@ -193,7 = +194,8 @@ static int xen_pt_word_reg_write(XenPCIP=0A cfg_entry->data = =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);=0A =0A = /* create value for writing to I/O device register */=0A- *val =3D = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);=0A+ *val =3D = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask,=0A+ = throughable_mask);=0A =0A return 0;=0A }=0A@@ -210,7 = +212,8 @@ static int xen_pt_long_reg_write(XenPCIP=0A cfg_entry->data = =3D XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);=0A =0A = /* create value for writing to I/O device register */=0A- *val =3D = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);=0A+ *val =3D = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask,=0A+ = throughable_mask);=0A =0A return 0;=0A }=0A@@ -611,6 = +614,7 @@ static XenPTRegInfo xen_pt_emu_reg_heade=0A .init_val = =3D 0x0000,=0A .res_mask =3D 0x0007,=0A .ro_mask =3D = 0x06F8,=0A+ .rw1c_mask =3D 0xF900,=0A .emu_mask =3D = 0x0010,=0A .init =3D xen_pt_status_reg_init,=0A = .u.w.read =3D xen_pt_word_reg_read,=0A@@ -910,6 +914,7 @@ static = XenPTRegInfo xen_pt_emu_reg_pcie[=0A .size =3D 2,=0A = .res_mask =3D 0xFFC0,=0A .ro_mask =3D 0x0030,=0A+ = .rw1c_mask =3D 0x000F,=0A .init =3D xen_pt_common_reg_init,= =0A .u.w.read =3D xen_pt_word_reg_read,=0A .u.w.write = =3D xen_pt_word_reg_write,=0A@@ -930,6 +935,7 @@ static XenPTRegInfo = xen_pt_emu_reg_pcie[=0A .offset =3D PCI_EXP_LNKSTA,=0A = .size =3D 2,=0A .ro_mask =3D 0x3FFF,=0A+ .rw1c_mask= =3D 0xC000,=0A .init =3D xen_pt_common_reg_init,=0A = .u.w.read =3D xen_pt_word_reg_read,=0A .u.w.write =3D = xen_pt_word_reg_write,=0A@@ -966,26 +972,6 @@ static XenPTRegInfo = xen_pt_emu_reg_pcie[=0A * Power Management Capability=0A */=0A =0A-/* = write Power Management Control/Status register */=0A-static int xen_pt_pmcs= r_reg_write(XenPCIPassthroughState *s,=0A- = XenPTReg *cfg_entry, uint16_t *val,=0A- = uint16_t dev_value, uint16_t valid_mask)=0A-{=0A- XenPTRegInfo *reg =3D = cfg_entry->reg;=0A- uint16_t writable_mask =3D 0;=0A- uint16_t = throughable_mask =3D get_throughable_mask(s, reg, valid_mask);=0A-=0A- = /* modify emulate register */=0A- writable_mask =3D reg->emu_mask & = ~reg->ro_mask & valid_mask;=0A- cfg_entry->data =3D XEN_PT_MERGE_VALUE(*= val, cfg_entry->data, writable_mask);=0A-=0A- /* create value for = writing to I/O device register */=0A- *val =3D XEN_PT_MERGE_VALUE(*val, = dev_value & ~PCI_PM_CTRL_PME_STATUS,=0A- = throughable_mask);=0A-=0A- return 0;=0A-}=0A-=0A /* Power Management = Capability reg static information table */=0A static XenPTRegInfo = xen_pt_emu_reg_pm[] =3D {=0A /* Next Pointer reg */=0A@@ -1016,11 = +1002,12 @@ static XenPTRegInfo xen_pt_emu_reg_pm[] =0A .size = =3D 2,=0A .init_val =3D 0x0008,=0A .res_mask =3D = 0x00F0,=0A- .ro_mask =3D 0xE10C,=0A+ .ro_mask =3D = 0x610C,=0A+ .rw1c_mask =3D 0x8000,=0A .emu_mask =3D = 0x810B,=0A .init =3D xen_pt_common_reg_init,=0A = .u.w.read =3D xen_pt_word_reg_read,=0A- .u.w.write =3D xen_pt_pmc= sr_reg_write,=0A+ .u.w.write =3D xen_pt_word_reg_write,=0A = },=0A {=0A .size =3D 0,=0A --=__PartC2F6EB1E.1__= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel --=__PartC2F6EB1E.1__=--