From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753223AbbFKKoA (ORCPT ); Thu, 11 Jun 2015 06:44:00 -0400 Received: from mail-pa0-f41.google.com ([209.85.220.41]:32842 "EHLO mail-pa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751905AbbFKKnw (ORCPT ); Thu, 11 Jun 2015 06:43:52 -0400 Message-ID: <55796660.1070702@samsung.com> Date: Thu, 11 Jun 2015 19:43:44 +0900 From: Krzysztof Kozlowski User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-Version: 1.0 To: Kukjin Kim , Sylwester Nawrocki , Tomasz Figa , Mike Turquette , Stephen Boyd , Marek Szyprowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH 1/2] clk: exynos4: Add PCLK_ADC gate clock on Exynos4x12 References: <1434011190-24563-1-git-send-email-k.kozlowski@samsung.com> In-Reply-To: <1434011190-24563-1-git-send-email-k.kozlowski@samsung.com> Content-Type: text/plain; charset=iso-8859-2 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org W dniu 11.06.2015 o 17:26, Krzysztof Kozlowski pisze: > Add proper gate clock for the Analog to Digital Converter (ADC) on > Exynos4x12. > > Signed-off-by: Krzysztof Kozlowski > --- > drivers/clk/samsung/clk-exynos4.c | 3 +++ > include/dt-bindings/clock/exynos4.h | 5 ++++- > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c > index 714d6ba782c8..5f32410a01f8 100644 > --- a/drivers/clk/samsung/clk-exynos4.c > +++ b/drivers/clk/samsung/clk-exynos4.c > @@ -85,6 +85,7 @@ > #define DIV_PERIL4 0xc560 > #define DIV_PERIL5 0xc564 > #define E4X12_DIV_CAM1 0xc568 > +#define E4X12_GATE_BUS_FSYS1 0xc744 > #define GATE_SCLK_CAM 0xc820 > #define GATE_IP_CAM 0xc920 > #define GATE_IP_TV 0xc924 > @@ -1095,6 +1096,8 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { > 0), > GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0, > 0), > + GATE(CLK_PCLK_ADC, "pclk_adc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, > + 0), Now I have even simpler idea. Don't add new clock id but just define here the CLK_TSADC as: GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0); With this change the second patch wouldn't be needed however this does not reflect the Exynos 4x12 datasheet. Any comments? Best regards, Krzysztof > GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), > GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), > GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, > diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h > index c4b1676ea674..4548531736c1 100644 > --- a/include/dt-bindings/clock/exynos4.h > +++ b/include/dt-bindings/clock/exynos4.h > @@ -268,7 +268,10 @@ > #define CLK_DIV_GDL 459 > #define CLK_DIV_GDR 460 > > +/* Exynos4x12 only */ > +#define CLK_PCLK_ADC 461 > + > /* must be greater than maximal clock id */ > -#define CLK_NR_CLKS 461 > +#define CLK_NR_CLKS 462 > > #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ > From mboxrd@z Thu Jan 1 00:00:00 1970 From: k.kozlowski@samsung.com (Krzysztof Kozlowski) Date: Thu, 11 Jun 2015 19:43:44 +0900 Subject: [PATCH 1/2] clk: exynos4: Add PCLK_ADC gate clock on Exynos4x12 In-Reply-To: <1434011190-24563-1-git-send-email-k.kozlowski@samsung.com> References: <1434011190-24563-1-git-send-email-k.kozlowski@samsung.com> Message-ID: <55796660.1070702@samsung.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org W dniu 11.06.2015 o 17:26, Krzysztof Kozlowski pisze: > Add proper gate clock for the Analog to Digital Converter (ADC) on > Exynos4x12. > > Signed-off-by: Krzysztof Kozlowski > --- > drivers/clk/samsung/clk-exynos4.c | 3 +++ > include/dt-bindings/clock/exynos4.h | 5 ++++- > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c > index 714d6ba782c8..5f32410a01f8 100644 > --- a/drivers/clk/samsung/clk-exynos4.c > +++ b/drivers/clk/samsung/clk-exynos4.c > @@ -85,6 +85,7 @@ > #define DIV_PERIL4 0xc560 > #define DIV_PERIL5 0xc564 > #define E4X12_DIV_CAM1 0xc568 > +#define E4X12_GATE_BUS_FSYS1 0xc744 > #define GATE_SCLK_CAM 0xc820 > #define GATE_IP_CAM 0xc920 > #define GATE_IP_TV 0xc924 > @@ -1095,6 +1096,8 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { > 0), > GATE(CLK_PPMUIMAGE, "ppmuimage", "aclk200", E4X12_GATE_IP_IMAGE, 9, 0, > 0), > + GATE(CLK_PCLK_ADC, "pclk_adc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, > + 0), Now I have even simpler idea. Don't add new clock id but just define here the CLK_TSADC as: GATE(CLK_TSADC, "tsadc", "aclk133", E4X12_GATE_BUS_FSYS1, 16, 0, 0); With this change the second patch wouldn't be needed however this does not reflect the Exynos 4x12 datasheet. Any comments? Best regards, Krzysztof > GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), > GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), > GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, > diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h > index c4b1676ea674..4548531736c1 100644 > --- a/include/dt-bindings/clock/exynos4.h > +++ b/include/dt-bindings/clock/exynos4.h > @@ -268,7 +268,10 @@ > #define CLK_DIV_GDL 459 > #define CLK_DIV_GDR 460 > > +/* Exynos4x12 only */ > +#define CLK_PCLK_ADC 461 > + > /* must be greater than maximal clock id */ > -#define CLK_NR_CLKS 461 > +#define CLK_NR_CLKS 462 > > #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ >