From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:40951)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <Yongbok.Kim@imgtec.com>) id 1Z7KBu-0008I7-3Y
	for qemu-devel@nongnu.org; Tue, 23 Jun 2015 05:08:26 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <Yongbok.Kim@imgtec.com>) id 1Z7KBq-00019U-Pf
	for qemu-devel@nongnu.org; Tue, 23 Jun 2015 05:08:26 -0400
Received: from mailapp01.imgtec.com ([195.59.15.196]:53758)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <Yongbok.Kim@imgtec.com>) id 1Z7KBq-00018a-KK
	for qemu-devel@nongnu.org; Tue, 23 Jun 2015 05:08:22 -0400
Message-ID: <55892202.7070207@imgtec.com>
Date: Tue, 23 Jun 2015 10:08:18 +0100
From: Yongbok Kim <yongbok.kim@imgtec.com>
MIME-Version: 1.0
References: <1434731138-4918-1-git-send-email-yongbok.kim@imgtec.com>
	<1434731138-4918-14-git-send-email-yongbok.kim@imgtec.com>
	<5587FD69.1030908@imgtec.com>
In-Reply-To: <5587FD69.1030908@imgtec.com>
Content-Type: text/plain; charset="windows-1252"
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] [PATCH v2 13/15] target-mips: microMIPS32 R6 Major
	instructions
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Leon Alrae <leon.alrae@imgtec.com>, qemu-devel@nongnu.org
Cc: aurelien@aurel32.net

On 22/06/2015 13:19, Leon Alrae wrote:
> On 19/06/2015 17:25, Yongbok Kim wrote:
>> @@ -14958,8 +14966,28 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
>>      do_cop1:
>>          gen_cop1_ldst(ctx, mips32_op, rt, rs, imm);
>>          break;
>> -    case ADDIUPC:
>> -        {
>> +    case ADDIUPC: /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
>> +        if (ctx->insn_flags & ISA_MIPS32R6) {
>> +            /* PCREL: ADDIUPC, AUIPC, ALUIPC, LWPC */
>> +            switch ((ctx->opcode >> 16) & 0x1f) {
>> +            case ADDIUPC_00 ... ADDIUPC_07:
>> +                gen_pcrel(ctx, OPC_ADDIUPC, ctx->pc & ~0x3, rt);
>> +                break;
>> +            case AUIPC:
>> +                gen_pcrel(ctx, OPC_AUIPC, ctx->pc, rt);
> 
> According to the manual you should pass "ctx->pc & ~0x3" here. Otherwise the
> patch looks good to me.
> 
> Leon
> 

That's weird to see that in the doc. I've checked the instruction and it
has been confirmed that the instruction is *not* clearing the bottom 2 bits
of the PC. This issue will be corrected in the next doc release.

Regards,
Yongbok