From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56012) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z7P6q-0001tG-8P for qemu-devel@nongnu.org; Tue, 23 Jun 2015 10:23:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z7P6l-0004Dt-9V for qemu-devel@nongnu.org; Tue, 23 Jun 2015 10:23:32 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:64971) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z7P6l-0004Do-4N for qemu-devel@nongnu.org; Tue, 23 Jun 2015 10:23:27 -0400 Message-ID: <55896BD9.3060008@imgtec.com> Date: Tue, 23 Jun 2015 15:23:21 +0100 From: Leon Alrae MIME-Version: 1.0 References: <1434731138-4918-1-git-send-email-yongbok.kim@imgtec.com> <1434731138-4918-13-git-send-email-yongbok.kim@imgtec.com> In-Reply-To: <1434731138-4918-13-git-send-email-yongbok.kim@imgtec.com> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 12/15] target-mips: microMIPS32 R6 POOL32{I, C} instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim , qemu-devel@nongnu.org Cc: aurelien@aurel32.net On 19/06/2015 17:25, Yongbok Kim wrote: > add new microMIPS32 Release 6 POOL32I/POOL32C type instructions > > Signed-off-by: Yongbok Kim > --- > target-mips/translate.c | 31 +++++++++++++++++++++++++------ > 1 files changed, 25 insertions(+), 6 deletions(-) > > diff --git a/target-mips/translate.c b/target-mips/translate.c > index 5f6ae43..54c14b6 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -14652,9 +14652,18 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) > check_insn_opc_removed(ctx, ISA_MIPS32R6); > mips32_op = OPC_TGEIU; > goto do_trapi; > - case TNEI: > - mips32_op = OPC_TNEI; > - goto do_trapi; > + case TNEI: /* SYNCI */ > + if (ctx->insn_flags & ISA_MIPS32R6) { > + /* SYNCI */ > + /* Break the TB to be able to sync copied instructions > + immediately */ > + ctx->bstate = BS_STOP; > + } else { > + /* TNEI */ > + mips32_op = OPC_TNEI; > + goto do_trapi; > + } > + break; > case TEQI: > check_insn_opc_removed(ctx, ISA_MIPS32R6); > mips32_op = OPC_TEQI; > @@ -14784,23 +14793,33 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) > mips32_op = OPC_LL; > goto do_ld_lr; > do_ld_lr: > - gen_ld(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12)); > + offset = sextract32(ctx->opcode, 0, > + (ctx->insn_flags & ISA_MIPS32R6) ? 9 : 12); > + gen_ld(ctx, mips32_op, rt, rs, offset); > break; > do_st_lr: > gen_st(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12)); > break; > case SC: > - gen_st_cond(ctx, OPC_SC, rt, rs, SIMM(ctx->opcode, 0, 12)); > + offset = sextract32(ctx->opcode, 0, > + (ctx->insn_flags & ISA_MIPS32R6) ? 9 : 12); > + gen_st_cond(ctx, OPC_SC, rt, rs, offset); > break; > #if defined(TARGET_MIPS64) > case SCD: > check_insn(ctx, ISA_MIPS3); > check_mips_64(ctx); > - gen_st_cond(ctx, OPC_SCD, rt, rs, SIMM(ctx->opcode, 0, 12)); > + offset = sextract32(ctx->opcode, 0, > + (ctx->insn_flags & ISA_MIPS32R6) ? 9 : 12); What I meant earlier was offset calculated at the beginning of case POOL32C just once for the whole family of these instructions rather than individually. Thanks, Leon > + gen_st_cond(ctx, OPC_SCD, rt, rs, offset); > break; > #endif > case PREF: > /* Treat as no-op */ > + if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >= 24)) { > + /* hint codes 24-31 are reserved and signal RI */ > + generate_exception(ctx, EXCP_RI); > + } > break; > default: > MIPS_INVAL("pool32c"); >