From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753810AbbGJIfw (ORCPT ); Fri, 10 Jul 2015 04:35:52 -0400 Received: from mailout4.w1.samsung.com ([210.118.77.14]:10975 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753368AbbGJIfg (ORCPT ); Fri, 10 Jul 2015 04:35:36 -0400 X-AuditID: cbfec7f4-f79c56d0000012ee-cf-559f83d6905d Message-id: <559F83D6.8040409@samsung.com> Date: Fri, 10 Jul 2015 17:35:34 +0900 From: Krzysztof Kozlowski User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.7.0 MIME-version: 1.0 To: Bartlomiej Zolnierkiewicz , Thomas Abraham , Sylwester Nawrocki , Michael Turquette , Kukjin Kim , Kukjin Kim , Viresh Kumar Cc: Tomasz Figa , Lukasz Majewski , Heiko Stuebner , Chanwoo Choi , Kevin Hilman , Javier Martinez Canillas , Tobias Jakobi , Anand Moon , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Doug Anderson , Andreas Faerber Subject: Re: [PATCH v2 5/7] ARM: dts: Exynos4x12: add CPU OPP and regulator supply property References: <1436456621-29839-1-git-send-email-b.zolnierkie@samsung.com> <1436456621-29839-6-git-send-email-b.zolnierkie@samsung.com> In-reply-to: <1436456621-29839-6-git-send-email-b.zolnierkie@samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA01RfSyUcRzf756XexyXn8vLb1paV5rQlbT106Im9LSyqbHJ1nTxDOW43YOl 2tK8xSjLJp1CurzVMneVyGwO1yLjyNUkJlPNy2RobXnJQy3/fb6f1z++DCEzkc5MXEISp0lQ xstpCdm1/GZgjyW9LGxfbxXE6Xoe1xfXUfjD/DcKd1e20njlyySFLb+LaTz53Qvnlw/Q+PbY JIEX2qoBnho1AKwfs1B4Nm+Ywv1N92k8l98OcHFPiwg/qx8UY3NnIG6byqbwzUqAs578oHBt 0yLA9QvsUSd25mOmmC1JM5PsUkkmwTZqP4tZfW0OzQ5ZmmnWoLvOLpvE7K3ntYBtsJQSrKHr KjundwmxiZAcjubi41I4zV6/85LYmso2sfqe7+XFPAtIA+WKXMAwCB5ApUXOucBqFTqi3uE6 OhdIGBl8DFBLV/XfYxygF1XtYiEghe5oZcRHCJDQFfW1ZpACpqE3MlTpaAE7wHA03f9WJGAp tEO/CodJocce1olQvnlwrZSAL0n0sKQTCK7N8ByabxgC62vZAN3Vja4JVvAEytKP0MIyARVo xOwu0ATchgxPp4kCALUbRrT/XdoNrnJA1AIHLjlKzV+IUXkpeKWKT06IUUQlqvRg/bvzr8Aj 0yEjgAyQ20hD6LIwGaVM4VNVRoAYQm4vtUWrlDRamXqF0yRGapLjOd4ItjCk3En6oGkmVAZj lEncJY5Tc5p/qoixck4Du12CT2ulzjdm/V0b82MCrL2tjzkqigJJO1mHZ6av2sfWdCciKLJg fHtFjteZqHcex+M8jKEB5llqkxsO6/D3cytY5MO/9k2ePRKsc+/JWcoIeu8hl0+s7Gi8lrP/ U3P961PNop87dzFDBtWEp6Tm4kH6eIVam+fW0l3oZzmp2yon+Villzuh4ZV/AH4b3l/ZAgAA Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10.07.2015 00:43, Bartlomiej Zolnierkiewicz wrote: > For Exynos4x12 platforms, add CPU operating points (using > opp-v2 bindings) and CPU regulator supply properties for > migrating from Exynos specific cpufreq driver to using > generic cpufreq driver. > > Based on the earlier work by Thomas Abraham. > > Cc: Kukjin Kim > Cc: Doug Anderson > Cc: Javier Martinez Canillas > Cc: Andreas Faerber > Cc: Thomas Abraham > Signed-off-by: Bartlomiej Zolnierkiewicz > --- > arch/arm/boot/dts/exynos4212.dtsi | 81 ++++++++++++++++++++++++ > arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 4 ++ > arch/arm/boot/dts/exynos4412-origen.dts | 5 ++ > arch/arm/boot/dts/exynos4412-trats2.dts | 5 ++ > arch/arm/boot/dts/exynos4412.dtsi | 83 +++++++++++++++++++++++++ > 5 files changed, 178 insertions(+) > > diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi > index d9c8efee..9dc40d5 100644 > --- a/arch/arm/boot/dts/exynos4212.dtsi > +++ b/arch/arm/boot/dts/exynos4212.dtsi > @@ -30,6 +30,9 @@ > device_type = "cpu"; > compatible = "arm,cortex-a9"; > reg = <0xA00>; > + clocks = <&clock CLK_ARM_CLK>; > + clock-names = "cpu"; > + operating-points-v2 = <&cpu0_opp_table>; > cooling-min-level = <13>; > cooling-max-level = <7>; > #cooling-cells = <2>; /* min followed by max */ > @@ -39,6 +42,84 @@ > device_type = "cpu"; > compatible = "arm,cortex-a9"; > reg = <0xA01>; > + operating-points-v2 = <&cpu0_opp_table>; > + }; > + }; > + > + cpu0_opp_table: opp_table0 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp00 { > + opp-hz = <200000000>; > + opp-microvolt = <900000>; > + clock-latency-ns = <200000>; > + }; > + opp01 { > + opp-hz = <300000000>; > + opp-microvolt = <900000>; > + clock-latency-ns = <200000>; > + }; > + opp02 { > + opp-hz = <400000000>; > + opp-microvolt = <925000>; > + clock-latency-ns = <200000>; > + }; > + opp03 { > + opp-hz = <500000000>; > + opp-microvolt = <950000>; > + clock-latency-ns = <200000>; > + }; > + opp04 { > + opp-hz = <600000000>; > + opp-microvolt = <975000>; > + clock-latency-ns = <200000>; > + }; > + opp05 { > + opp-hz = <700000000>; > + opp-microvolt = <987500>; > + clock-latency-ns = <200000>; > + }; > + opp06 { > + opp-hz = <800000000>; > + opp-microvolt = <1000000>; > + clock-latency-ns = <200000>; > + }; > + opp07 { > + opp-hz = <900000000>; > + opp-microvolt = <1037500>; > + clock-latency-ns = <200000>; > + }; > + opp08 { > + opp-hz = <1000000000>; > + opp-microvolt = <1087500>; > + clock-latency-ns = <200000>; > + }; > + opp09 { > + opp-hz = <1100000000>; > + opp-microvolt = <1137500>; > + clock-latency-ns = <200000>; > + }; > + opp10 { > + opp-hz = <1200000000>; > + opp-microvolt = <1187500>; > + clock-latency-ns = <200000>; > + }; > + opp11 { > + opp-hz = <1300000000>; > + opp-microvolt = <1250000>; > + clock-latency-ns = <200000>; > + }; > + opp12 { > + opp-hz = <1400000000>; > + opp-microvolt = <1287500>; > + clock-latency-ns = <200000>; > + }; > + opp13 { > + opp-hz = <1500000000>; > + opp-microvolt = <1350000>; > + clock-latency-ns = <200000>; > + turbo-mode; > }; > }; > }; > diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi > index ca7d168..1c7811a 100644 > --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi > +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi > @@ -507,3 +507,7 @@ > &watchdog { > status = "okay"; > }; > + > +&cpu0 { > + cpu0-supply = <&buck2_reg>; > +}; Can you put this in alphabetical order (before ehci node)? > diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts > index 84c7631..21150b4 100644 > --- a/arch/arm/boot/dts/exynos4412-origen.dts > +++ b/arch/arm/boot/dts/exynos4412-origen.dts > @@ -532,3 +532,8 @@ > &watchdog { > status = "okay"; > }; > + > + > +&cpu0 { > + cpu0-supply = <&buck2_reg>; > +}; Ditto > diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts > index afc199d..1ee43456 100644 > --- a/arch/arm/boot/dts/exynos4412-trats2.dts > +++ b/arch/arm/boot/dts/exynos4412-trats2.dts > @@ -1313,3 +1313,8 @@ > vtmu-supply = <&ldo10_reg>; > status = "okay"; > }; > + > + > +&cpu0 { > + cpu0-supply = <&buck2_reg>; > +}; The same. Rest looks fine, so with the re-ordering: Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof > diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi > index b78ada7..cead3a7 100644 > --- a/arch/arm/boot/dts/exynos4412.dtsi > +++ b/arch/arm/boot/dts/exynos4412.dtsi > @@ -30,6 +30,9 @@ > device_type = "cpu"; > compatible = "arm,cortex-a9"; > reg = <0xA00>; > + clocks = <&clock CLK_ARM_CLK>; > + clock-names = "cpu"; > + operating-points-v2 = <&cpu0_opp_table>; > cooling-min-level = <13>; > cooling-max-level = <7>; > #cooling-cells = <2>; /* min followed by max */ > @@ -39,18 +42,98 @@ > device_type = "cpu"; > compatible = "arm,cortex-a9"; > reg = <0xA01>; > + operating-points-v2 = <&cpu0_opp_table>; > }; > > cpu@A02 { > device_type = "cpu"; > compatible = "arm,cortex-a9"; > reg = <0xA02>; > + operating-points-v2 = <&cpu0_opp_table>; > }; > > cpu@A03 { > device_type = "cpu"; > compatible = "arm,cortex-a9"; > reg = <0xA03>; > + operating-points-v2 = <&cpu0_opp_table>; > + }; > + }; > + > + cpu0_opp_table: opp_table0 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp00 { > + opp-hz = <200000000>; > + opp-microvolt = <900000>; > + clock-latency-ns = <200000>; > + }; > + opp01 { > + opp-hz = <300000000>; > + opp-microvolt = <900000>; > + clock-latency-ns = <200000>; > + }; > + opp02 { > + opp-hz = <400000000>; > + opp-microvolt = <925000>; > + clock-latency-ns = <200000>; > + }; > + opp03 { > + opp-hz = <500000000>; > + opp-microvolt = <950000>; > + clock-latency-ns = <200000>; > + }; > + opp04 { > + opp-hz = <600000000>; > + opp-microvolt = <975000>; > + clock-latency-ns = <200000>; > + }; > + opp05 { > + opp-hz = <700000000>; > + opp-microvolt = <987500>; > + clock-latency-ns = <200000>; > + }; > + opp06 { > + opp-hz = <800000000>; > + opp-microvolt = <1000000>; > + clock-latency-ns = <200000>; > + }; > + opp07 { > + opp-hz = <900000000>; > + opp-microvolt = <1037500>; > + clock-latency-ns = <200000>; > + }; > + opp08 { > + opp-hz = <1000000000>; > + opp-microvolt = <1087500>; > + clock-latency-ns = <200000>; > + }; > + opp09 { > + opp-hz = <1100000000>; > + opp-microvolt = <1137500>; > + clock-latency-ns = <200000>; > + }; > + opp10 { > + opp-hz = <1200000000>; > + opp-microvolt = <1187500>; > + clock-latency-ns = <200000>; > + }; > + opp11 { > + opp-hz = <1300000000>; > + opp-microvolt = <1250000>; > + clock-latency-ns = <200000>; > + }; > + opp12 { > + opp-hz = <1400000000>; > + opp-microvolt = <1287500>; > + clock-latency-ns = <200000>; > + }; > + opp13 { > + opp-hz = <1500000000>; > + opp-microvolt = <1350000>; > + clock-latency-ns = <200000>; > + turbo-mode; > }; > }; > > From mboxrd@z Thu Jan 1 00:00:00 1970 From: k.kozlowski@samsung.com (Krzysztof Kozlowski) Date: Fri, 10 Jul 2015 17:35:34 +0900 Subject: [PATCH v2 5/7] ARM: dts: Exynos4x12: add CPU OPP and regulator supply property In-Reply-To: <1436456621-29839-6-git-send-email-b.zolnierkie@samsung.com> References: <1436456621-29839-1-git-send-email-b.zolnierkie@samsung.com> <1436456621-29839-6-git-send-email-b.zolnierkie@samsung.com> Message-ID: <559F83D6.8040409@samsung.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 10.07.2015 00:43, Bartlomiej Zolnierkiewicz wrote: > For Exynos4x12 platforms, add CPU operating points (using > opp-v2 bindings) and CPU regulator supply properties for > migrating from Exynos specific cpufreq driver to using > generic cpufreq driver. > > Based on the earlier work by Thomas Abraham. > > Cc: Kukjin Kim > Cc: Doug Anderson > Cc: Javier Martinez Canillas > Cc: Andreas Faerber > Cc: Thomas Abraham > Signed-off-by: Bartlomiej Zolnierkiewicz > --- > arch/arm/boot/dts/exynos4212.dtsi | 81 ++++++++++++++++++++++++ > arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 4 ++ > arch/arm/boot/dts/exynos4412-origen.dts | 5 ++ > arch/arm/boot/dts/exynos4412-trats2.dts | 5 ++ > arch/arm/boot/dts/exynos4412.dtsi | 83 +++++++++++++++++++++++++ > 5 files changed, 178 insertions(+) > > diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi > index d9c8efee..9dc40d5 100644 > --- a/arch/arm/boot/dts/exynos4212.dtsi > +++ b/arch/arm/boot/dts/exynos4212.dtsi > @@ -30,6 +30,9 @@ > device_type = "cpu"; > compatible = "arm,cortex-a9"; > reg = <0xA00>; > + clocks = <&clock CLK_ARM_CLK>; > + clock-names = "cpu"; > + operating-points-v2 = <&cpu0_opp_table>; > cooling-min-level = <13>; > cooling-max-level = <7>; > #cooling-cells = <2>; /* min followed by max */ > @@ -39,6 +42,84 @@ > device_type = "cpu"; > compatible = "arm,cortex-a9"; > reg = <0xA01>; > + operating-points-v2 = <&cpu0_opp_table>; > + }; > + }; > + > + cpu0_opp_table: opp_table0 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp00 { > + opp-hz = <200000000>; > + opp-microvolt = <900000>; > + clock-latency-ns = <200000>; > + }; > + opp01 { > + opp-hz = <300000000>; > + opp-microvolt = <900000>; > + clock-latency-ns = <200000>; > + }; > + opp02 { > + opp-hz = <400000000>; > + opp-microvolt = <925000>; > + clock-latency-ns = <200000>; > + }; > + opp03 { > + opp-hz = <500000000>; > + opp-microvolt = <950000>; > + clock-latency-ns = <200000>; > + }; > + opp04 { > + opp-hz = <600000000>; > + opp-microvolt = <975000>; > + clock-latency-ns = <200000>; > + }; > + opp05 { > + opp-hz = <700000000>; > + opp-microvolt = <987500>; > + clock-latency-ns = <200000>; > + }; > + opp06 { > + opp-hz = <800000000>; > + opp-microvolt = <1000000>; > + clock-latency-ns = <200000>; > + }; > + opp07 { > + opp-hz = <900000000>; > + opp-microvolt = <1037500>; > + clock-latency-ns = <200000>; > + }; > + opp08 { > + opp-hz = <1000000000>; > + opp-microvolt = <1087500>; > + clock-latency-ns = <200000>; > + }; > + opp09 { > + opp-hz = <1100000000>; > + opp-microvolt = <1137500>; > + clock-latency-ns = <200000>; > + }; > + opp10 { > + opp-hz = <1200000000>; > + opp-microvolt = <1187500>; > + clock-latency-ns = <200000>; > + }; > + opp11 { > + opp-hz = <1300000000>; > + opp-microvolt = <1250000>; > + clock-latency-ns = <200000>; > + }; > + opp12 { > + opp-hz = <1400000000>; > + opp-microvolt = <1287500>; > + clock-latency-ns = <200000>; > + }; > + opp13 { > + opp-hz = <1500000000>; > + opp-microvolt = <1350000>; > + clock-latency-ns = <200000>; > + turbo-mode; > }; > }; > }; > diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi > index ca7d168..1c7811a 100644 > --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi > +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi > @@ -507,3 +507,7 @@ > &watchdog { > status = "okay"; > }; > + > +&cpu0 { > + cpu0-supply = <&buck2_reg>; > +}; Can you put this in alphabetical order (before ehci node)? > diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts > index 84c7631..21150b4 100644 > --- a/arch/arm/boot/dts/exynos4412-origen.dts > +++ b/arch/arm/boot/dts/exynos4412-origen.dts > @@ -532,3 +532,8 @@ > &watchdog { > status = "okay"; > }; > + > + > +&cpu0 { > + cpu0-supply = <&buck2_reg>; > +}; Ditto > diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts > index afc199d..1ee43456 100644 > --- a/arch/arm/boot/dts/exynos4412-trats2.dts > +++ b/arch/arm/boot/dts/exynos4412-trats2.dts > @@ -1313,3 +1313,8 @@ > vtmu-supply = <&ldo10_reg>; > status = "okay"; > }; > + > + > +&cpu0 { > + cpu0-supply = <&buck2_reg>; > +}; The same. Rest looks fine, so with the re-ordering: Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof > diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi > index b78ada7..cead3a7 100644 > --- a/arch/arm/boot/dts/exynos4412.dtsi > +++ b/arch/arm/boot/dts/exynos4412.dtsi > @@ -30,6 +30,9 @@ > device_type = "cpu"; > compatible = "arm,cortex-a9"; > reg = <0xA00>; > + clocks = <&clock CLK_ARM_CLK>; > + clock-names = "cpu"; > + operating-points-v2 = <&cpu0_opp_table>; > cooling-min-level = <13>; > cooling-max-level = <7>; > #cooling-cells = <2>; /* min followed by max */ > @@ -39,18 +42,98 @@ > device_type = "cpu"; > compatible = "arm,cortex-a9"; > reg = <0xA01>; > + operating-points-v2 = <&cpu0_opp_table>; > }; > > cpu at A02 { > device_type = "cpu"; > compatible = "arm,cortex-a9"; > reg = <0xA02>; > + operating-points-v2 = <&cpu0_opp_table>; > }; > > cpu at A03 { > device_type = "cpu"; > compatible = "arm,cortex-a9"; > reg = <0xA03>; > + operating-points-v2 = <&cpu0_opp_table>; > + }; > + }; > + > + cpu0_opp_table: opp_table0 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp00 { > + opp-hz = <200000000>; > + opp-microvolt = <900000>; > + clock-latency-ns = <200000>; > + }; > + opp01 { > + opp-hz = <300000000>; > + opp-microvolt = <900000>; > + clock-latency-ns = <200000>; > + }; > + opp02 { > + opp-hz = <400000000>; > + opp-microvolt = <925000>; > + clock-latency-ns = <200000>; > + }; > + opp03 { > + opp-hz = <500000000>; > + opp-microvolt = <950000>; > + clock-latency-ns = <200000>; > + }; > + opp04 { > + opp-hz = <600000000>; > + opp-microvolt = <975000>; > + clock-latency-ns = <200000>; > + }; > + opp05 { > + opp-hz = <700000000>; > + opp-microvolt = <987500>; > + clock-latency-ns = <200000>; > + }; > + opp06 { > + opp-hz = <800000000>; > + opp-microvolt = <1000000>; > + clock-latency-ns = <200000>; > + }; > + opp07 { > + opp-hz = <900000000>; > + opp-microvolt = <1037500>; > + clock-latency-ns = <200000>; > + }; > + opp08 { > + opp-hz = <1000000000>; > + opp-microvolt = <1087500>; > + clock-latency-ns = <200000>; > + }; > + opp09 { > + opp-hz = <1100000000>; > + opp-microvolt = <1137500>; > + clock-latency-ns = <200000>; > + }; > + opp10 { > + opp-hz = <1200000000>; > + opp-microvolt = <1187500>; > + clock-latency-ns = <200000>; > + }; > + opp11 { > + opp-hz = <1300000000>; > + opp-microvolt = <1250000>; > + clock-latency-ns = <200000>; > + }; > + opp12 { > + opp-hz = <1400000000>; > + opp-microvolt = <1287500>; > + clock-latency-ns = <200000>; > + }; > + opp13 { > + opp-hz = <1500000000>; > + opp-microvolt = <1350000>; > + clock-latency-ns = <200000>; > + turbo-mode; > }; > }; > >