Re: [PATCH] i2c: davinci: Fix bus rate calculation on Keystone SoC

[Sekhar Nori <nsekhar-l0cyMroinI0@public.gmane.org>]

On Friday 10 July 2015 01:23 AM, Wolfram Sang wrote:
> On Thu, Jun 18, 2015 at 12:22:33PM -0400, Murali Karicheri wrote:
>> On 06/18/2015 05:00 AM, Sekhar Nori wrote:
>>> On Thursday 18 June 2015 02:23 PM, Alexander Sverdlin wrote:
>>>> According to KeyStone Architecture I2C User Guide,
>>>>
>>>>                          module clock frequency
>>>> master clock frequency = ----------------------
>>>>                          (ICCL + 6) + (ICCH + 6)
>>>>
>>>> i.e. "d" in i2c_davinci_calc_clk_dividers() should be fixed and
>>>> not dependent from module clock prescaler PSC on these SoCs.
>>>>
>>>> Signed-off-by: Alexander Sverdlin <alexander.sverdlin-xNZwKgViW5gAvxtiuMwx3w@public.gmane.org>
>>>> ---
>>>>
>>>> RFC: If someone from TI has an idea how to improve the coverage of future Keystone
>>>> revisions -- hints/patches are welcome. The current ID check is based on
>>>> Davinci/Keystone datasheets and is at least working on real Keystone II.
>>>
>>> + Murali who works on Keystone devices in TI.
>>
>> + Grygorii
>>
>> + Grygorii has been involved in the Keystone related enhancement and
>> reviewing prior patches. Need to have his ack for this change
> 
> Any news?

Fixing Grygorii's e-mail id.

Grygorii, let me know if you don't have the thread. I can forward.

Thanks,
Sekhar