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From: Richard Henderson <rth@twiddle.net>
To: Aurelien Jarno <aurelien@aurel32.net>, qemu-devel@nongnu.org
Cc: Leon Alrae <leon.alrae@imgtec.com>
Subject: Re: [Qemu-devel] [PATCH v2] target-mips: simplify LWL/LDL mask generation
Date: Thu, 23 Jul 2015 13:51:40 -0700	[thread overview]
Message-ID: <55B153DC.6010307@twiddle.net> (raw)
In-Reply-To: <1436972709-5860-1-git-send-email-aurelien@aurel32.net>

On 07/15/2015 08:05 AM, Aurelien Jarno wrote:
> The LWL/LDL instructions mask the GPR with a mask depending on the
> address alignement. It is currently computed by doing:
> 
>     mask = 0x7fffffffffffffffull >> (t1 ^ 63)
> 
> It's simpler to generate it by doing:
> 
>     mask = ~(-1 << t1)
> 
> It uses one TCG instruction less, and it avoids a 32/64-bit constant
> loading which can take a few instructions on RISC hosts.
> 
> Cc: Leon Alrae <leon.alrae@imgtec.com>
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> ---
>  target-mips/translate.c | 14 ++++++--------
>  1 file changed, 6 insertions(+), 8 deletions(-)
> 
> Changes v1 -> v2:
> - Use ~(-1 << t1) instead of (1 << t1) - 1 as suggested by Paolo
>   Bonzini.

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~

      reply	other threads:[~2015-07-23 20:51 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-15 15:05 [Qemu-devel] [PATCH v2] target-mips: simplify LWL/LDL mask generation Aurelien Jarno
2015-07-23 20:51 ` Richard Henderson [this message]

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