* [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions
@ 2015-08-24 16:17 Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 01/33] linux-user: tilegx: Firstly add architecture related features Richard Henderson
` (32 more replies)
0 siblings, 33 replies; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
I've flushed out the v13 I posted last Thursday to handle all the
instructions required to execute Hello World. In the process I
found a number of bugs and design flaws in v13, and reshaped the
translation a bit to better handle insns with no register outputs.
Please review.
After this, I would hope that Chen Gang will follow up to implement
the rest of the instructions that he has identified running the
gcc testsuite, and then start in on the floating point.
r~
Chen Gang (9):
linux-user: tilegx: Firstly add architecture related features
linux-user: Support tilegx architecture in linux-user
linux-user: Conditionalize syscalls which are not defined in tilegx
target-tilegx: Add opcode basic implementation from Tilera Corporation
target-tilegx: Modify opcode_tilegx.h to fit QEMU usage
target-tilegx: Add special register information from Tilera
Corporation
target-tilegx: Add cpu basic features for linux-user
target-tilegx: Add several helpers for instructions translation
target-tilegx: Add TILE-Gx building files
Richard Henderson (24):
target-tilegx: Modify _SPECIAL_ opcodes
target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1
target-tilegx: Framework for decoding bundles
target-tilegx: Generate SEGV properly
target-tilegx: Handle simple logical operations
target-tilegx: Handle arithmetic instructions
target-tilegx: Handle most bit manipulation instructions
target-tilegx: Handle basic load and store instructions
target-tilegx: Handle post-increment load and store instructions
target-tilegx: Handle unconditional jump instructions
target-tilegx: Handle conditional branch instructions
target-tilegx: Handle comparison instructions
target-tilegx: Implement system and memory management instructions
target-tilegx: Handle bitfield instructions
target-tilegx: Handle shift instructions
target-tilegx: Handle conditional move instructions
target-tilegx: Handle scalar multiply instructions
target-tilegx: Handle mask instructions
target-tilegx: Handle v1cmpeq, v1cmpne
target-tilegx: Handle mtspr, mfspr
target-tilegx: Handle atomic instructions
target-tilegx: Handle v4int_l/h
target-tilegx: Handle v1shli, v1shrui
target-tilegx: Handle v1shl, v1shru, v1shrs
configure | 2 +
default-configs/tilegx-linux-user.mak | 1 +
include/elf.h | 2 +
linux-user/elfload.c | 23 +
linux-user/main.c | 298 +++++
linux-user/syscall.c | 50 +-
linux-user/syscall_defs.h | 14 +-
linux-user/tilegx/syscall.h | 40 +
linux-user/tilegx/syscall_nr.h | 324 +++++
linux-user/tilegx/target_cpu.h | 35 +
linux-user/tilegx/target_signal.h | 28 +
linux-user/tilegx/target_structs.h | 46 +
linux-user/tilegx/termbits.h | 274 +++++
target-tilegx/Makefile.objs | 1 +
target-tilegx/cpu.c | 173 +++
target-tilegx/cpu.h | 177 +++
target-tilegx/helper.c | 93 ++
target-tilegx/helper.h | 10 +
target-tilegx/opcode_tilegx.h | 1406 ++++++++++++++++++++++
target-tilegx/simd_helper.c | 63 +
target-tilegx/spr_def_64.h | 216 ++++
target-tilegx/translate.c | 2135 +++++++++++++++++++++++++++++++++
22 files changed, 5405 insertions(+), 6 deletions(-)
create mode 100644 default-configs/tilegx-linux-user.mak
create mode 100644 linux-user/tilegx/syscall.h
create mode 100644 linux-user/tilegx/syscall_nr.h
create mode 100644 linux-user/tilegx/target_cpu.h
create mode 100644 linux-user/tilegx/target_signal.h
create mode 100644 linux-user/tilegx/target_structs.h
create mode 100644 linux-user/tilegx/termbits.h
create mode 100644 target-tilegx/Makefile.objs
create mode 100644 target-tilegx/cpu.c
create mode 100644 target-tilegx/cpu.h
create mode 100644 target-tilegx/helper.c
create mode 100644 target-tilegx/helper.h
create mode 100644 target-tilegx/opcode_tilegx.h
create mode 100644 target-tilegx/simd_helper.c
create mode 100644 target-tilegx/spr_def_64.h
create mode 100644 target-tilegx/translate.c
--
2.4.3
^ permalink raw reply [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 01/33] linux-user: tilegx: Firstly add architecture related features
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 02/33] linux-user: Support tilegx architecture in linux-user Richard Henderson
` (31 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, Chen Gang, xili_gchen_5257, peter.maydell
From: Chen Gang <xili_gchen_5257@hotmail.com>
They are based on Linux kernel tilegx architecture for 64 bit binary,
and also based on tilegx ABI reference document, and also reference from
other targets implementations.
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <BLU436-SMTP2508945F92945BB525605A3B9660@phx.gbl>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
linux-user/tilegx/syscall.h | 40 +++++
linux-user/tilegx/syscall_nr.h | 324 +++++++++++++++++++++++++++++++++++++
linux-user/tilegx/target_cpu.h | 35 ++++
linux-user/tilegx/target_signal.h | 28 ++++
linux-user/tilegx/target_structs.h | 46 ++++++
linux-user/tilegx/termbits.h | 274 +++++++++++++++++++++++++++++++
6 files changed, 747 insertions(+)
create mode 100644 linux-user/tilegx/syscall.h
create mode 100644 linux-user/tilegx/syscall_nr.h
create mode 100644 linux-user/tilegx/target_cpu.h
create mode 100644 linux-user/tilegx/target_signal.h
create mode 100644 linux-user/tilegx/target_structs.h
create mode 100644 linux-user/tilegx/termbits.h
diff --git a/linux-user/tilegx/syscall.h b/linux-user/tilegx/syscall.h
new file mode 100644
index 0000000..653ece1
--- /dev/null
+++ b/linux-user/tilegx/syscall.h
@@ -0,0 +1,40 @@
+#ifndef TILEGX_SYSCALLS_H
+#define TILEGX_SYSCALLS_H
+
+#define UNAME_MACHINE "tilegx"
+#define UNAME_MINIMUM_RELEASE "3.19"
+
+#define MMAP_SHIFT TARGET_PAGE_BITS
+
+#define TILEGX_IS_ERRNO(ret) \
+ ((ret) > 0xfffffffffffff000ULL) /* errno is 0 -- 4096 */
+
+typedef uint64_t tilegx_reg_t;
+
+struct target_pt_regs {
+
+ union {
+ /* Saved main processor registers; 56..63 are special. */
+ tilegx_reg_t regs[56];
+ struct {
+ tilegx_reg_t __regs[53];
+ tilegx_reg_t tp; /* aliases regs[TREG_TP] */
+ tilegx_reg_t sp; /* aliases regs[TREG_SP] */
+ tilegx_reg_t lr; /* aliases regs[TREG_LR] */
+ };
+ };
+
+ /* Saved special registers. */
+ tilegx_reg_t pc; /* stored in EX_CONTEXT_K_0 */
+ tilegx_reg_t ex1; /* stored in EX_CONTEXT_K_1 (PL and ICS bit) */
+ tilegx_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */
+ tilegx_reg_t orig_r0; /* r0 at syscall entry, else zero */
+ tilegx_reg_t flags; /* flags (see below) */
+ tilegx_reg_t cmpexch; /* value of CMPEXCH_VALUE SPR at interrupt */
+ tilegx_reg_t pad[2];
+};
+
+#define TARGET_MLOCKALL_MCL_CURRENT 1
+#define TARGET_MLOCKALL_MCL_FUTURE 2
+
+#endif
diff --git a/linux-user/tilegx/syscall_nr.h b/linux-user/tilegx/syscall_nr.h
new file mode 100644
index 0000000..1dca348
--- /dev/null
+++ b/linux-user/tilegx/syscall_nr.h
@@ -0,0 +1,324 @@
+#ifndef TILEGX_SYSCALL_NR
+#define TILEGX_SYSCALL_NR
+
+/*
+ * Copy from linux kernel asm-generic/unistd.h, which tilegx uses.
+ */
+#define TARGET_NR_io_setup 0
+#define TARGET_NR_io_destroy 1
+#define TARGET_NR_io_submit 2
+#define TARGET_NR_io_cancel 3
+#define TARGET_NR_io_getevents 4
+#define TARGET_NR_setxattr 5
+#define TARGET_NR_lsetxattr 6
+#define TARGET_NR_fsetxattr 7
+#define TARGET_NR_getxattr 8
+#define TARGET_NR_lgetxattr 9
+#define TARGET_NR_fgetxattr 10
+#define TARGET_NR_listxattr 11
+#define TARGET_NR_llistxattr 12
+#define TARGET_NR_flistxattr 13
+#define TARGET_NR_removexattr 14
+#define TARGET_NR_lremovexattr 15
+#define TARGET_NR_fremovexattr 16
+#define TARGET_NR_getcwd 17
+#define TARGET_NR_lookup_dcookie 18
+#define TARGET_NR_eventfd2 19
+#define TARGET_NR_epoll_create1 20
+#define TARGET_NR_epoll_ctl 21
+#define TARGET_NR_epoll_pwait 22
+#define TARGET_NR_dup 23
+#define TARGET_NR_dup3 24
+#define TARGET_NR_fcntl 25
+#define TARGET_NR_inotify_init1 26
+#define TARGET_NR_inotify_add_watch 27
+#define TARGET_NR_inotify_rm_watch 28
+#define TARGET_NR_ioctl 29
+#define TARGET_NR_ioprio_set 30
+#define TARGET_NR_ioprio_get 31
+#define TARGET_NR_flock 32
+#define TARGET_NR_mknodat 33
+#define TARGET_NR_mkdirat 34
+#define TARGET_NR_unlinkat 35
+#define TARGET_NR_symlinkat 36
+#define TARGET_NR_linkat 37
+#define TARGET_NR_renameat 38
+#define TARGET_NR_umount2 39
+#define TARGET_NR_mount 40
+#define TARGET_NR_pivot_root 41
+#define TARGET_NR_nfsservctl 42
+#define TARGET_NR_statfs 43
+#define TARGET_NR_fstatfs 44
+#define TARGET_NR_truncate 45
+#define TARGET_NR_ftruncate 46
+#define TARGET_NR_fallocate 47
+#define TARGET_NR_faccessat 48
+#define TARGET_NR_chdir 49
+#define TARGET_NR_fchdir 50
+#define TARGET_NR_chroot 51
+#define TARGET_NR_fchmod 52
+#define TARGET_NR_fchmodat 53
+#define TARGET_NR_fchownat 54
+#define TARGET_NR_fchown 55
+#define TARGET_NR_openat 56
+#define TARGET_NR_close 57
+#define TARGET_NR_vhangup 58
+#define TARGET_NR_pipe2 59
+#define TARGET_NR_quotactl 60
+#define TARGET_NR_getdents64 61
+#define TARGET_NR_lseek 62
+#define TARGET_NR_read 63
+#define TARGET_NR_write 64
+#define TARGET_NR_readv 65
+#define TARGET_NR_writev 66
+#define TARGET_NR_pread64 67
+#define TARGET_NR_pwrite64 68
+#define TARGET_NR_preadv 69
+#define TARGET_NR_pwritev 70
+#define TARGET_NR_sendfile 71
+#define TARGET_NR_pselect6 72
+#define TARGET_NR_ppoll 73
+#define TARGET_NR_signalfd4 74
+#define TARGET_NR_vmsplice 75
+#define TARGET_NR_splice 76
+#define TARGET_NR_tee 77
+#define TARGET_NR_readlinkat 78
+#define TARGET_NR_fstatat64 79 /* let syscall.c known */
+#define TARGET_NR_fstat 80
+#define TARGET_NR_sync 81
+#define TARGET_NR_fsync 82
+#define TARGET_NR_fdatasync 83
+#define TARGET_NR_sync_file_range 84 /* For tilegx, no range2 */
+#define TARGET_NR_timerfd_create 85
+#define TARGET_NR_timerfd_settime 86
+#define TARGET_NR_timerfd_gettime 87
+#define TARGET_NR_utimensat 88
+#define TARGET_NR_acct 89
+#define TARGET_NR_capget 90
+#define TARGET_NR_capset 91
+#define TARGET_NR_personality 92
+#define TARGET_NR_exit 93
+#define TARGET_NR_exit_group 94
+#define TARGET_NR_waitid 95
+#define TARGET_NR_set_tid_address 96
+#define TARGET_NR_unshare 97
+#define TARGET_NR_futex 98
+#define TARGET_NR_set_robust_list 99
+#define TARGET_NR_get_robust_list 100
+#define TARGET_NR_nanosleep 101
+#define TARGET_NR_getitimer 102
+#define TARGET_NR_setitimer 103
+#define TARGET_NR_kexec_load 104
+#define TARGET_NR_init_module 105
+#define TARGET_NR_delete_module 106
+#define TARGET_NR_timer_create 107
+#define TARGET_NR_timer_gettime 108
+#define TARGET_NR_timer_getoverrun 109
+#define TARGET_NR_timer_settime 110
+#define TARGET_NR_timer_delete 111
+#define TARGET_NR_clock_settime 112
+#define TARGET_NR_clock_gettime 113
+#define TARGET_NR_clock_getres 114
+#define TARGET_NR_clock_nanosleep 115
+#define TARGET_NR_syslog 116
+#define TARGET_NR_ptrace 117
+#define TARGET_NR_sched_setparam 118
+#define TARGET_NR_sched_setscheduler 119
+#define TARGET_NR_sched_getscheduler 120
+#define TARGET_NR_sched_getparam 121
+#define TARGET_NR_sched_setaffinity 122
+#define TARGET_NR_sched_getaffinity 123
+#define TARGET_NR_sched_yield 124
+#define TARGET_NR_sched_get_priority_max 125
+#define TARGET_NR_sched_get_priority_min 126
+#define TARGET_NR_sched_rr_get_interval 127
+#define TARGET_NR_restart_syscall 128
+#define TARGET_NR_kill 129
+#define TARGET_NR_tkill 130
+#define TARGET_NR_tgkill 131
+#define TARGET_NR_sigaltstack 132
+#define TARGET_NR_rt_sigsuspend 133
+#define TARGET_NR_rt_sigaction 134
+#define TARGET_NR_rt_sigprocmask 135
+#define TARGET_NR_rt_sigpending 136
+#define TARGET_NR_rt_sigtimedwait 137
+#define TARGET_NR_rt_sigqueueinfo 138
+#define TARGET_NR_rt_sigreturn 139
+#define TARGET_NR_setpriority 140
+#define TARGET_NR_getpriority 141
+#define TARGET_NR_reboot 142
+#define TARGET_NR_setregid 143
+#define TARGET_NR_setgid 144
+#define TARGET_NR_setreuid 145
+#define TARGET_NR_setuid 146
+#define TARGET_NR_setresuid 147
+#define TARGET_NR_getresuid 148
+#define TARGET_NR_setresgid 149
+#define TARGET_NR_getresgid 150
+#define TARGET_NR_setfsuid 151
+#define TARGET_NR_setfsgid 152
+#define TARGET_NR_times 153
+#define TARGET_NR_setpgid 154
+#define TARGET_NR_getpgid 155
+#define TARGET_NR_getsid 156
+#define TARGET_NR_setsid 157
+#define TARGET_NR_getgroups 158
+#define TARGET_NR_setgroups 159
+#define TARGET_NR_uname 160
+#define TARGET_NR_sethostname 161
+#define TARGET_NR_setdomainname 162
+#define TARGET_NR_getrlimit 163
+#define TARGET_NR_setrlimit 164
+#define TARGET_NR_getrusage 165
+#define TARGET_NR_umask 166
+#define TARGET_NR_prctl 167
+#define TARGET_NR_getcpu 168
+#define TARGET_NR_gettimeofday 169
+#define TARGET_NR_settimeofday 170
+#define TARGET_NR_adjtimex 171
+#define TARGET_NR_getpid 172
+#define TARGET_NR_getppid 173
+#define TARGET_NR_getuid 174
+#define TARGET_NR_geteuid 175
+#define TARGET_NR_getgid 176
+#define TARGET_NR_getegid 177
+#define TARGET_NR_gettid 178
+#define TARGET_NR_sysinfo 179
+#define TARGET_NR_mq_open 180
+#define TARGET_NR_mq_unlink 181
+#define TARGET_NR_mq_timedsend 182
+#define TARGET_NR_mq_timedreceive 183
+#define TARGET_NR_mq_notify 184
+#define TARGET_NR_mq_getsetattr 185
+#define TARGET_NR_msgget 186
+#define TARGET_NR_msgctl 187
+#define TARGET_NR_msgrcv 188
+#define TARGET_NR_msgsnd 189
+#define TARGET_NR_semget 190
+#define TARGET_NR_semctl 191
+#define TARGET_NR_semtimedop 192
+#define TARGET_NR_semop 193
+#define TARGET_NR_shmget 194
+#define TARGET_NR_shmctl 195
+#define TARGET_NR_shmat 196
+#define TARGET_NR_shmdt 197
+#define TARGET_NR_socket 198
+#define TARGET_NR_socketpair 199
+#define TARGET_NR_bind 200
+#define TARGET_NR_listen 201
+#define TARGET_NR_accept 202
+#define TARGET_NR_connect 203
+#define TARGET_NR_getsockname 204
+#define TARGET_NR_getpeername 205
+#define TARGET_NR_sendto 206
+#define TARGET_NR_recvfrom 207
+#define TARGET_NR_setsockopt 208
+#define TARGET_NR_getsockopt 209
+#define TARGET_NR_shutdown 210
+#define TARGET_NR_sendmsg 211
+#define TARGET_NR_recvmsg 212
+#define TARGET_NR_readahead 213
+#define TARGET_NR_brk 214
+#define TARGET_NR_munmap 215
+#define TARGET_NR_mremap 216
+#define TARGET_NR_add_key 217
+#define TARGET_NR_request_key 218
+#define TARGET_NR_keyctl 219
+#define TARGET_NR_clone 220
+#define TARGET_NR_execve 221
+#define TARGET_NR_mmap 222
+#define TARGET_NR_fadvise64 223
+#define TARGET_NR_swapon 224
+#define TARGET_NR_swapoff 225
+#define TARGET_NR_mprotect 226
+#define TARGET_NR_msync 227
+#define TARGET_NR_mlock 228
+#define TARGET_NR_munlock 229
+#define TARGET_NR_mlockall 230
+#define TARGET_NR_munlockall 231
+#define TARGET_NR_mincore 232
+#define TARGET_NR_madvise 233
+#define TARGET_NR_remap_file_pages 234
+#define TARGET_NR_mbind 235
+#define TARGET_NR_get_mempolicy 236
+#define TARGET_NR_set_mempolicy 237
+#define TARGET_NR_migrate_pages 238
+#define TARGET_NR_move_pages 239
+#define TARGET_NR_rt_tgsigqueueinfo 240
+#define TARGET_NR_perf_event_open 241
+#define TARGET_NR_accept4 242
+#define TARGET_NR_recvmmsg 243
+
+#define TARGET_NR_arch_specific_syscall 244
+#define TARGET_NR_cacheflush 245 /* tilegx own syscall */
+
+#define TARGET_NR_wait4 260
+#define TARGET_NR_prlimit64 261
+#define TARGET_NR_fanotify_init 262
+#define TARGET_NR_fanotify_mark 263
+#define TARGET_NR_name_to_handle_at 264
+#define TARGET_NR_open_by_handle_at 265
+#define TARGET_NR_clock_adjtime 266
+#define TARGET_NR_syncfs 267
+#define TARGET_NR_setns 268
+#define TARGET_NR_sendmmsg 269
+#define TARGET_NR_process_vm_readv 270
+#define TARGET_NR_process_vm_writev 271
+#define TARGET_NR_kcmp 272
+#define TARGET_NR_finit_module 273
+#define TARGET_NR_sched_setattr 274
+#define TARGET_NR_sched_getattr 275
+#define TARGET_NR_renameat2 276
+#define TARGET_NR_seccomp 277
+#define TARGET_NR_getrandom 278
+#define TARGET_NR_memfd_create 279
+#define TARGET_NR_bpf 280
+#define TARGET_NR_execveat 281
+
+#define TARGET_NR_open 1024
+#define TARGET_NR_link 1025
+#define TARGET_NR_unlink 1026
+#define TARGET_NR_mknod 1027
+#define TARGET_NR_chmod 1028
+#define TARGET_NR_chown 1029
+#define TARGET_NR_mkdir 1030
+#define TARGET_NR_rmdir 1031
+#define TARGET_NR_lchown 1032
+#define TARGET_NR_access 1033
+#define TARGET_NR_rename 1034
+#define TARGET_NR_readlink 1035
+#define TARGET_NR_symlink 1036
+#define TARGET_NR_utimes 1037
+#define TARGET_NR_stat64 1038 /* let syscall.c known */
+#define TARGET_NR_lstat 1039
+
+#define TARGET_NR_pipe 1040
+#define TARGET_NR_dup2 1041
+#define TARGET_NR_epoll_create 1042
+#define TARGET_NR_inotify_init 1043
+#define TARGET_NR_eventfd 1044
+#define TARGET_NR_signalfd 1045
+
+#define TARGET_NR_alarm 1059
+#define TARGET_NR_getpgrp 1060
+#define TARGET_NR_pause 1061
+#define TARGET_NR_time 1062
+#define TARGET_NR_utime 1063
+#define TARGET_NR_creat 1064
+#define TARGET_NR_getdents 1065
+#define TARGET_NR_futimesat 1066
+#define TARGET_NR_select 1067
+#define TARGET_NR_poll 1068
+#define TARGET_NR_epoll_wait 1069
+#define TARGET_NR_ustat 1070
+#define TARGET_NR_vfork 1071
+#define TARGET_NR_oldwait4 1072
+#define TARGET_NR_recv 1073
+#define TARGET_NR_send 1074
+#define TARGET_NR_bdflush 1075
+#define TARGET_NR_umount 1076
+#define TARGET_NR_uselib 1077
+#define TARGET_NR__sysctl 1078
+#define TARGET_NR_fork 1079
+
+#endif
diff --git a/linux-user/tilegx/target_cpu.h b/linux-user/tilegx/target_cpu.h
new file mode 100644
index 0000000..c96e81d
--- /dev/null
+++ b/linux-user/tilegx/target_cpu.h
@@ -0,0 +1,35 @@
+/*
+ * TILE-Gx specific CPU ABI and functions for linux-user
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef TARGET_CPU_H
+#define TARGET_CPU_H
+
+static inline void cpu_clone_regs(CPUTLGState *env, target_ulong newsp)
+{
+ if (newsp) {
+ env->regs[TILEGX_R_SP] = newsp;
+ }
+ env->regs[TILEGX_R_RE] = 0;
+}
+
+static inline void cpu_set_tls(CPUTLGState *env, target_ulong newtls)
+{
+ env->regs[TILEGX_R_TP] = newtls;
+}
+
+#endif
diff --git a/linux-user/tilegx/target_signal.h b/linux-user/tilegx/target_signal.h
new file mode 100644
index 0000000..b595f98
--- /dev/null
+++ b/linux-user/tilegx/target_signal.h
@@ -0,0 +1,28 @@
+#ifndef TARGET_SIGNAL_H
+#define TARGET_SIGNAL_H
+
+#include "cpu.h"
+
+/* this struct defines a stack used during syscall handling */
+
+typedef struct target_sigaltstack {
+ abi_ulong ss_sp;
+ abi_int ss_flags;
+ abi_ulong ss_size;
+} target_stack_t;
+
+/*
+ * sigaltstack controls
+ */
+#define TARGET_SS_ONSTACK 1
+#define TARGET_SS_DISABLE 2
+
+#define TARGET_MINSIGSTKSZ 2048
+#define TARGET_SIGSTKSZ 8192
+
+static inline abi_ulong get_sp_from_cpustate(CPUTLGState *state)
+{
+ return state->regs[TILEGX_R_SP];
+}
+
+#endif /* TARGET_SIGNAL_H */
diff --git a/linux-user/tilegx/target_structs.h b/linux-user/tilegx/target_structs.h
new file mode 100644
index 0000000..7d3ff78
--- /dev/null
+++ b/linux-user/tilegx/target_structs.h
@@ -0,0 +1,46 @@
+/*
+ * TILE-Gx specific structures for linux-user
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef TARGET_STRUCTS_H
+#define TARGET_STRUCTS_H
+
+struct target_ipc_perm {
+ abi_int __key; /* Key. */
+ abi_uint uid; /* Owner's user ID. */
+ abi_uint gid; /* Owner's group ID. */
+ abi_uint cuid; /* Creator's user ID. */
+ abi_uint cgid; /* Creator's group ID. */
+ abi_uint mode; /* Read/write permission. */
+ abi_ushort __seq; /* Sequence number. */
+};
+
+struct target_shmid_ds {
+ struct target_ipc_perm shm_perm; /* operation permission struct */
+ abi_long shm_segsz; /* size of segment in bytes */
+ abi_ulong shm_atime; /* time of last shmat() */
+ abi_ulong shm_dtime; /* time of last shmdt() */
+ abi_ulong shm_ctime; /* time of last change by shmctl() */
+ abi_int shm_cpid; /* pid of creator */
+ abi_int shm_lpid; /* pid of last shmop */
+ abi_ushort shm_nattch; /* number of current attaches */
+ abi_ushort shm_unused; /* compatibility */
+ abi_ulong __unused4;
+ abi_ulong __unused5;
+};
+
+#endif
diff --git a/linux-user/tilegx/termbits.h b/linux-user/tilegx/termbits.h
new file mode 100644
index 0000000..91ec236
--- /dev/null
+++ b/linux-user/tilegx/termbits.h
@@ -0,0 +1,274 @@
+#ifndef TILEGX_TERMBITS_H
+#define TILEGX_TERMBITS_H
+
+/* From asm-generic/termbits.h, which is used by tilegx */
+
+#define TARGET_NCCS 19
+struct target_termios {
+ unsigned int c_iflag; /* input mode flags */
+ unsigned int c_oflag; /* output mode flags */
+ unsigned int c_cflag; /* control mode flags */
+ unsigned int c_lflag; /* local mode flags */
+ unsigned char c_line; /* line discipline */
+ unsigned char c_cc[TARGET_NCCS]; /* control characters */
+};
+
+struct target_termios2 {
+ unsigned int c_iflag; /* input mode flags */
+ unsigned int c_oflag; /* output mode flags */
+ unsigned int c_cflag; /* control mode flags */
+ unsigned int c_lflag; /* local mode flags */
+ unsigned char c_line; /* line discipline */
+ unsigned char c_cc[TARGET_NCCS]; /* control characters */
+ unsigned int c_ispeed; /* input speed */
+ unsigned int c_ospeed; /* output speed */
+};
+
+/* c_cc characters */
+#define TARGET_VINTR 0
+#define TARGET_VQUIT 1
+#define TARGET_VERASE 2
+#define TARGET_VKILL 3
+#define TARGET_VEOF 4
+#define TARGET_VTIME 5
+#define TARGET_VMIN 6
+#define TARGET_VSWTC 7
+#define TARGET_VSTART 8
+#define TARGET_VSTOP 9
+#define TARGET_VSUSP 10
+#define TARGET_VEOL 11
+#define TARGET_VREPRINT 12
+#define TARGET_VDISCARD 13
+#define TARGET_VWERASE 14
+#define TARGET_VLNEXT 15
+#define TARGET_VEOL2 16
+
+/* c_iflag bits */
+#define TARGET_IGNBRK 0000001
+#define TARGET_BRKINT 0000002
+#define TARGET_IGNPAR 0000004
+#define TARGET_PARMRK 0000010
+#define TARGET_INPCK 0000020
+#define TARGET_ISTRIP 0000040
+#define TARGET_INLCR 0000100
+#define TARGET_IGNCR 0000200
+#define TARGET_ICRNL 0000400
+#define TARGET_IUCLC 0001000
+#define TARGET_IXON 0002000
+#define TARGET_IXANY 0004000
+#define TARGET_IXOFF 0010000
+#define TARGET_IMAXBEL 0020000
+#define TARGET_IUTF8 0040000
+
+/* c_oflag bits */
+#define TARGET_OPOST 0000001
+#define TARGET_OLCUC 0000002
+#define TARGET_ONLCR 0000004
+#define TARGET_OCRNL 0000010
+#define TARGET_ONOCR 0000020
+#define TARGET_ONLRET 0000040
+#define TARGET_OFILL 0000100
+#define TARGET_OFDEL 0000200
+#define TARGET_NLDLY 0000400
+#define TARGET_NL0 0000000
+#define TARGET_NL1 0000400
+#define TARGET_CRDLY 0003000
+#define TARGET_CR0 0000000
+#define TARGET_CR1 0001000
+#define TARGET_CR2 0002000
+#define TARGET_CR3 0003000
+#define TARGET_TABDLY 0014000
+#define TARGET_TAB0 0000000
+#define TARGET_TAB1 0004000
+#define TARGET_TAB2 0010000
+#define TARGET_TAB3 0014000
+#define TARGET_XTABS 0014000
+#define TARGET_BSDLY 0020000
+#define TARGET_BS0 0000000
+#define TARGET_BS1 0020000
+#define TARGET_VTDLY 0040000
+#define TARGET_VT0 0000000
+#define TARGET_VT1 0040000
+#define TARGET_FFDLY 0100000
+#define TARGET_FF0 0000000
+#define TARGET_FF1 0100000
+
+/* c_cflag bit meaning */
+#define TARGET_CBAUD 0010017
+#define TARGET_B0 0000000 /* hang up */
+#define TARGET_B50 0000001
+#define TARGET_B75 0000002
+#define TARGET_B110 0000003
+#define TARGET_B134 0000004
+#define TARGET_B150 0000005
+#define TARGET_B200 0000006
+#define TARGET_B300 0000007
+#define TARGET_B600 0000010
+#define TARGET_B1200 0000011
+#define TARGET_B1800 0000012
+#define TARGET_B2400 0000013
+#define TARGET_B4800 0000014
+#define TARGET_B9600 0000015
+#define TARGET_B19200 0000016
+#define TARGET_B38400 0000017
+#define TARGET_EXTA TARGET_B19200
+#define TARGET_EXTB TARGET_B38400
+#define TARGET_CSIZE 0000060
+#define TARGET_CS5 0000000
+#define TARGET_CS6 0000020
+#define TARGET_CS7 0000040
+#define TARGET_CS8 0000060
+#define TARGET_CSTOPB 0000100
+#define TARGET_CREAD 0000200
+#define TARGET_PARENB 0000400
+#define TARGET_PARODD 0001000
+#define TARGET_HUPCL 0002000
+#define TARGET_CLOCAL 0004000
+#define TARGET_CBAUDEX 0010000
+#define TARGET_BOTHER 0010000
+#define TARGET_B57600 0010001
+#define TARGET_B115200 0010002
+#define TARGET_B230400 0010003
+#define TARGET_B460800 0010004
+#define TARGET_B500000 0010005
+#define TARGET_B576000 0010006
+#define TARGET_B921600 0010007
+#define TARGET_B1000000 0010010
+#define TARGET_B1152000 0010011
+#define TARGET_B1500000 0010012
+#define TARGET_B2000000 0010013
+#define TARGET_B2500000 0010014
+#define TARGET_B3000000 0010015
+#define TARGET_B3500000 0010016
+#define TARGET_B4000000 0010017
+#define TARGET_CIBAUD 002003600000 /* input baud rate */
+#define TARGET_CMSPAR 010000000000 /* mark or space (stick) parity */
+#define TARGET_CRTSCTS 020000000000 /* flow control */
+
+#define TARGET_IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
+
+/* c_lflag bits */
+#define TARGET_ISIG 0000001
+#define TARGET_ICANON 0000002
+#define TARGET_XCASE 0000004
+#define TARGET_ECHO 0000010
+#define TARGET_ECHOE 0000020
+#define TARGET_ECHOK 0000040
+#define TARGET_ECHONL 0000100
+#define TARGET_NOFLSH 0000200
+#define TARGET_TOSTOP 0000400
+#define TARGET_ECHOCTL 0001000
+#define TARGET_ECHOPRT 0002000
+#define TARGET_ECHOKE 0004000
+#define TARGET_FLUSHO 0010000
+#define TARGET_PENDIN 0040000
+#define TARGET_IEXTEN 0100000
+#define TARGET_EXTPROC 0200000
+
+/* tcflow() and TCXONC use these */
+#define TARGET_TCOOFF 0
+#define TARGET_TCOON 1
+#define TARGET_TCIOFF 2
+#define TARGET_TCION 3
+
+/* tcflush() and TCFLSH use these */
+#define TARGET_TCIFLUSH 0
+#define TARGET_TCOFLUSH 1
+#define TARGET_TCIOFLUSH 2
+
+/* tcsetattr uses these */
+#define TARGET_TCSANOW 0
+#define TARGET_TCSADRAIN 1
+#define TARGET_TCSAFLUSH 2
+
+/* From asm-generic/ioctls.h, which is used by tilegx */
+
+#define TARGET_TCGETS 0x5401
+#define TARGET_TCSETS 0x5402
+#define TARGET_TCSETSW 0x5403
+#define TARGET_TCSETSF 0x5404
+#define TARGET_TCGETA 0x5405
+#define TARGET_TCSETA 0x5406
+#define TARGET_TCSETAW 0x5407
+#define TARGET_TCSETAF 0x5408
+#define TARGET_TCSBRK 0x5409
+#define TARGET_TCXONC 0x540A
+#define TARGET_TCFLSH 0x540B
+#define TARGET_TIOCEXCL 0x540C
+#define TARGET_TIOCNXCL 0x540D
+#define TARGET_TIOCSCTTY 0x540E
+#define TARGET_TIOCGPGRP 0x540F
+#define TARGET_TIOCSPGRP 0x5410
+#define TARGET_TIOCOUTQ 0x5411
+#define TARGET_TIOCSTI 0x5412
+#define TARGET_TIOCGWINSZ 0x5413
+#define TARGET_TIOCSWINSZ 0x5414
+#define TARGET_TIOCMGET 0x5415
+#define TARGET_TIOCMBIS 0x5416
+#define TARGET_TIOCMBIC 0x5417
+#define TARGET_TIOCMSET 0x5418
+#define TARGET_TIOCGSOFTCAR 0x5419
+#define TARGET_TIOCSSOFTCAR 0x541A
+#define TARGET_FIONREAD 0x541B
+#define TARGET_TIOCINQ TARGET_FIONREAD
+#define TARGET_TIOCLINUX 0x541C
+#define TARGET_TIOCCONS 0x541D
+#define TARGET_TIOCGSERIAL 0x541E
+#define TARGET_TIOCSSERIAL 0x541F
+#define TARGET_TIOCPKT 0x5420
+#define TARGET_FIONBIO 0x5421
+#define TARGET_TIOCNOTTY 0x5422
+#define TARGET_TIOCSETD 0x5423
+#define TARGET_TIOCGETD 0x5424
+#define TARGET_TCSBRKP 0x5425
+#define TARGET_TIOCSBRK 0x5427
+#define TARGET_TIOCCBRK 0x5428
+#define TARGET_TIOCGSID 0x5429
+#define TARGET_TCGETS2 TARGET_IOR('T', 0x2A, struct termios2)
+#define TARGET_TCSETS2 TARGET_IOW('T', 0x2B, struct termios2)
+#define TARGET_TCSETSW2 TARGET_IOW('T', 0x2C, struct termios2)
+#define TARGET_TCSETSF2 TARGET_IOW('T', 0x2D, struct termios2)
+#define TARGET_TIOCGRS485 0x542E
+#define TARGET_TIOCSRS485 0x542F
+#define TARGET_TIOCGPTN TARGET_IOR('T', 0x30, unsigned int)
+#define TARGET_TIOCSPTLCK TARGET_IOW('T', 0x31, int)
+#define TARGET_TIOCGDEV TARGET_IOR('T', 0x32, unsigned int)
+#define TARGET_TCGETX 0x5432
+#define TARGET_TCSETX 0x5433
+#define TARGET_TCSETXF 0x5434
+#define TARGET_TCSETXW 0x5435
+#define TARGET_TIOCSIG TARGET_IOW('T', 0x36, int)
+#define TARGET_TIOCVHANGUP 0x5437
+#define TARGET_TIOCGPKT TARGET_IOR('T', 0x38, int)
+#define TARGET_TIOCGPTLCK TARGET_IOR('T', 0x39, int)
+#define TARGET_TIOCGEXCL TARGET_IOR('T', 0x40, int)
+
+#define TARGET_FIONCLEX 0x5450
+#define TARGET_FIOCLEX 0x5451
+#define TARGET_FIOASYNC 0x5452
+#define TARGET_TIOCSERCONFIG 0x5453
+#define TARGET_TIOCSERGWILD 0x5454
+#define TARGET_TIOCSERSWILD 0x5455
+#define TARGET_TIOCGLCKTRMIOS 0x5456
+#define TARGET_TIOCSLCKTRMIOS 0x5457
+#define TARGET_TIOCSERGSTRUCT 0x5458
+#define TARGET_TIOCSERGETLSR 0x5459
+#define TARGET_TIOCSERGETMULTI 0x545A
+#define TARGET_TIOCSERSETMULTI 0x545B
+
+#define TARGET_TIOCMIWAIT 0x545C
+#define TARGET_TIOCGICOUNT 0x545D
+#define TARGET_FIOQSIZE 0x5460
+
+#define TARGET_TIOCPKT_DATA 0
+#define TARGET_TIOCPKT_FLUSHREAD 1
+#define TARGET_TIOCPKT_FLUSHWRITE 2
+#define TARGET_TIOCPKT_STOP 4
+#define TARGET_TIOCPKT_START 8
+#define TARGET_TIOCPKT_NOSTOP 16
+#define TARGET_TIOCPKT_DOSTOP 32
+#define TARGET_TIOCPKT_IOCTL 64
+
+#define TARGET_TIOCSER_TEMT 0x01
+
+#endif
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 02/33] linux-user: Support tilegx architecture in linux-user
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 01/33] linux-user: tilegx: Firstly add architecture related features Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 03/33] linux-user: Conditionalize syscalls which are not defined in tilegx Richard Henderson
` (30 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, Chen Gang, xili_gchen_5257, peter.maydell
From: Chen Gang <xili_gchen_5257@hotmail.com>
Add main working flow feature, system call processing feature, and elf64
tilegx binary loading feature, based on Linux kernel tilegx 64-bit
implementation.
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <BLU436-SMTP938552D42808AA60634582B9660@phx.gbl>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
include/elf.h | 2 +
linux-user/elfload.c | 23 ++++
linux-user/main.c | 295 ++++++++++++++++++++++++++++++++++++++++++++++
linux-user/syscall_defs.h | 14 ++-
4 files changed, 329 insertions(+), 5 deletions(-)
diff --git a/include/elf.h b/include/elf.h
index 4afd474..79859f0 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -133,6 +133,8 @@ typedef int64_t Elf64_Sxword;
#define EM_AARCH64 183
+#define EM_TILEGX 191 /* TILE-Gx */
+
/* This is the info that is needed to parse the dynamic section of the file */
#define DT_NULL 0
#define DT_NEEDED 1
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 1788368..bfb8d1f 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1218,6 +1218,29 @@ static inline void init_thread(struct target_pt_regs *regs, struct image_info *i
#endif /* TARGET_S390X */
+#ifdef TARGET_TILEGX
+
+/* 42 bits real used address, a half for user mode */
+#define ELF_START_MMAP (0x00000020000000000ULL)
+
+#define elf_check_arch(x) ((x) == EM_TILEGX)
+
+#define ELF_CLASS ELFCLASS64
+#define ELF_DATA ELFDATA2LSB
+#define ELF_ARCH EM_TILEGX
+
+static inline void init_thread(struct target_pt_regs *regs,
+ struct image_info *infop)
+{
+ regs->pc = infop->entry;
+ regs->sp = infop->start_stack;
+
+}
+
+#define ELF_EXEC_PAGESIZE 65536 /* TILE-Gx page size is 64KB */
+
+#endif /* TARGET_TILEGX */
+
#ifndef ELF_PLATFORM
#define ELF_PLATFORM (NULL)
#endif
diff --git a/linux-user/main.c b/linux-user/main.c
index fdee981..2d4b0b4 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3411,6 +3411,290 @@ void cpu_loop(CPUS390XState *env)
#endif /* TARGET_S390X */
+#ifdef TARGET_TILEGX
+
+static void gen_sigsegv_mapper(CPUTLGState *env, target_ulong addr)
+{
+ target_siginfo_t info;
+
+ info.si_signo = TARGET_SIGSEGV;
+ info.si_errno = 0;
+ info.si_code = TARGET_SEGV_MAPERR;
+ info._sifields._sigfault._addr = addr;
+ queue_signal(env, info.si_signo, &info);
+}
+
+static void gen_sigill_reg(CPUTLGState *env)
+{
+ target_siginfo_t info;
+
+ info.si_signo = TARGET_SIGILL;
+ info.si_errno = 0;
+ info.si_code = TARGET_ILL_PRVREG;
+ info._sifields._sigfault._addr = env->pc;
+ queue_signal(env, info.si_signo, &info);
+}
+
+static int get_regval(CPUTLGState *env, uint8_t reg, target_ulong *val)
+{
+ if (likely(reg < TILEGX_R_COUNT)) {
+ *val = env->regs[reg];
+ return 0;
+ }
+
+ switch (reg) {
+ case TILEGX_R_SN:
+ case TILEGX_R_ZERO:
+ *val = 0;
+ return 0;
+ case TILEGX_R_IDN0:
+ case TILEGX_R_IDN1:
+ case TILEGX_R_UDN0:
+ case TILEGX_R_UDN1:
+ case TILEGX_R_UDN2:
+ case TILEGX_R_UDN3:
+ return -1;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static int set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
+{
+ if (unlikely(reg >= TILEGX_R_COUNT)) {
+ switch (reg) {
+ case TILEGX_R_SN:
+ case TILEGX_R_ZERO:
+ return 0;
+ case TILEGX_R_IDN0:
+ case TILEGX_R_IDN1:
+ case TILEGX_R_UDN0:
+ case TILEGX_R_UDN1:
+ case TILEGX_R_UDN2:
+ case TILEGX_R_UDN3:
+ return -1;
+ default:
+ g_assert_not_reached();
+ }
+ }
+
+ env->regs[reg] = val;
+ return 0;
+}
+
+/*
+ * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
+ * memory at the address held in the first source register. If the values are
+ * not equal, then no memory operation is performed. If the values are equal,
+ * the 8-byte quantity from the second source register is written into memory
+ * at the address held in the first source register. In either case, the result
+ * of the instruction is the value read from memory. The compare and write to
+ * memory are atomic and thus can be used for synchronization purposes. This
+ * instruction only operates for addresses aligned to a 8-byte boundary.
+ * Unaligned memory access causes an Unaligned Data Reference interrupt.
+ *
+ * Functional Description (64-bit)
+ * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
+ * rf[Dest] = memVal;
+ * if (memVal == SPR[CmpValueSPR])
+ * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
+ *
+ * Functional Description (32-bit)
+ * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
+ * rf[Dest] = memVal;
+ * if (memVal == signExtend32 (SPR[CmpValueSPR]))
+ * memoryWriteWord (rf[SrcA], rf[SrcB]);
+ *
+ *
+ * This function also processes exch and exch4 which need not process SPR.
+ */
+static void do_exch(CPUTLGState *env, bool quad, bool cmp)
+{
+ uint8_t rdst, rsrc, rsrcb;
+ target_ulong addr;
+ target_long val, sprval;
+
+ start_exclusive();
+
+ rdst = extract32(env->excparam, 16, 8);
+ rsrc = extract32(env->excparam, 8, 8);
+ rsrcb = extract32(env->excparam, 0, 8);
+
+ if (get_regval(env, rsrc, &addr)) {
+ goto sigill_reg;
+ }
+ if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
+ goto sigsegv_mapper;
+ }
+
+ if (cmp) {
+ if (quad) {
+ sprval = env->spregs[TILEGX_SPR_CMPEXCH];
+ } else {
+ sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
+ }
+ }
+
+ if (!cmp || val == sprval) {
+ target_long valb;
+
+ if (get_regval(env, rsrcb, (target_ulong *)&valb)) {
+ goto sigill_reg;
+ }
+ if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
+ goto sigsegv_mapper;
+ }
+ }
+
+ if (set_regval(env, rdst, val)) {
+ goto sigill_reg;
+ }
+ end_exclusive();
+ return;
+
+sigill_reg:
+ end_exclusive();
+ gen_sigill_reg(env);
+ return;
+
+sigsegv_mapper:
+ end_exclusive();
+ gen_sigsegv_mapper(env, addr);
+}
+
+static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
+{
+ uint8_t rdst, rsrc, rsrcb;
+ int8_t write = 1;
+ target_ulong addr;
+ target_long val, valb;
+
+ start_exclusive();
+
+ rdst = extract32(env->excparam, 16, 8);
+ rsrc = extract32(env->excparam, 8, 8);
+ rsrcb = extract32(env->excparam, 0, 8);
+
+
+ if (get_regval(env, rsrc, &addr)) {
+ goto sigill_reg;
+ }
+ if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
+ goto sigsegv_mapper;
+ }
+
+ if (get_regval(env, rsrcb, (target_ulong *)&valb)) {
+ goto sigill_reg;
+ }
+ switch (trapnr) {
+ case TILEGX_EXCP_OPCODE_FETCHADD:
+ case TILEGX_EXCP_OPCODE_FETCHADD4:
+ valb += val;
+ break;
+ case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
+ valb += val;
+ if (valb < 0) {
+ write = 0;
+ }
+ break;
+ case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
+ valb += val;
+ if ((int32_t)valb < 0) {
+ write = 0;
+ }
+ break;
+ case TILEGX_EXCP_OPCODE_FETCHAND:
+ case TILEGX_EXCP_OPCODE_FETCHAND4:
+ valb &= val;
+ break;
+ case TILEGX_EXCP_OPCODE_FETCHOR:
+ case TILEGX_EXCP_OPCODE_FETCHOR4:
+ valb |= val;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if (write) {
+ if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
+ goto sigsegv_mapper;
+ }
+ }
+
+ if (set_regval(env, rdst, val)) {
+ goto sigill_reg;
+ }
+ end_exclusive();
+ return;
+
+sigill_reg:
+ end_exclusive();
+ gen_sigill_reg(env);
+ return;
+
+sigsegv_mapper:
+ end_exclusive();
+ gen_sigsegv_mapper(env, addr);
+}
+
+void cpu_loop(CPUTLGState *env)
+{
+ CPUState *cs = CPU(tilegx_env_get_cpu(env));
+ int trapnr;
+
+ while (1) {
+ cpu_exec_start(cs);
+ trapnr = cpu_tilegx_exec(cs);
+ cpu_exec_end(cs);
+ switch (trapnr) {
+ case TILEGX_EXCP_SYSCALL:
+ env->regs[TILEGX_R_RE] = do_syscall(env, env->regs[TILEGX_R_NR],
+ env->regs[0], env->regs[1],
+ env->regs[2], env->regs[3],
+ env->regs[4], env->regs[5],
+ env->regs[6], env->regs[7]);
+ env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(env->regs[TILEGX_R_RE])
+ ? - env->regs[TILEGX_R_RE]
+ : 0;
+ break;
+ case TILEGX_EXCP_OPCODE_EXCH:
+ do_exch(env, true, false);
+ break;
+ case TILEGX_EXCP_OPCODE_EXCH4:
+ do_exch(env, false, false);
+ break;
+ case TILEGX_EXCP_OPCODE_CMPEXCH:
+ do_exch(env, true, true);
+ break;
+ case TILEGX_EXCP_OPCODE_CMPEXCH4:
+ do_exch(env, false, true);
+ break;
+ case TILEGX_EXCP_OPCODE_FETCHADD:
+ case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
+ case TILEGX_EXCP_OPCODE_FETCHAND:
+ case TILEGX_EXCP_OPCODE_FETCHOR:
+ do_fetch(env, trapnr, true);
+ break;
+ case TILEGX_EXCP_OPCODE_FETCHADD4:
+ case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
+ case TILEGX_EXCP_OPCODE_FETCHAND4:
+ case TILEGX_EXCP_OPCODE_FETCHOR4:
+ do_fetch(env, trapnr, false);
+ break;
+ case TILEGX_EXCP_REG_IDN_ACCESS:
+ case TILEGX_EXCP_REG_UDN_ACCESS:
+ gen_sigill_reg(env);
+ break;
+ default:
+ fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
+ g_assert_not_reached();
+ }
+ process_pending_signals(env);
+ }
+}
+
+#endif
+
THREAD CPUState *thread_cpu;
void task_settid(TaskState *ts)
@@ -4386,6 +4670,17 @@ int main(int argc, char **argv, char **envp)
env->psw.mask = regs->psw.mask;
env->psw.addr = regs->psw.addr;
}
+#elif defined(TARGET_TILEGX)
+ {
+ int i;
+ for (i = 0; i < TILEGX_R_COUNT; i++) {
+ env->regs[i] = regs->regs[i];
+ }
+ for (i = 0; i < TILEGX_SPR_COUNT; i++) {
+ env->spregs[i] = 0;
+ }
+ env->pc = regs->pc;
+ }
#else
#error unsupported target CPU
#endif
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index edd5f3c..e6af073 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user/syscall_defs.h
@@ -64,8 +64,9 @@
#endif
#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SH4) \
- || defined(TARGET_M68K) || defined(TARGET_CRIS) || defined(TARGET_UNICORE32) \
- || defined(TARGET_S390X) || defined(TARGET_OPENRISC)
+ || defined(TARGET_M68K) || defined(TARGET_CRIS) \
+ || defined(TARGET_UNICORE32) || defined(TARGET_S390X) \
+ || defined(TARGET_OPENRISC) || defined(TARGET_TILEGX)
#define TARGET_IOC_SIZEBITS 14
#define TARGET_IOC_DIRBITS 2
@@ -365,7 +366,8 @@ int do_sigaction(int sig, const struct target_sigaction *act,
|| defined(TARGET_PPC) || defined(TARGET_MIPS) || defined(TARGET_SH4) \
|| defined(TARGET_M68K) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) \
|| defined(TARGET_MICROBLAZE) || defined(TARGET_UNICORE32) \
- || defined(TARGET_S390X) || defined(TARGET_OPENRISC)
+ || defined(TARGET_S390X) || defined(TARGET_OPENRISC) \
+ || defined(TARGET_TILEGX)
#if defined(TARGET_SPARC)
#define TARGET_SA_NOCLDSTOP 8u
@@ -1871,7 +1873,7 @@ struct target_stat {
abi_ulong target_st_ctime_nsec;
unsigned int __unused[2];
};
-#elif defined(TARGET_OPENRISC)
+#elif defined(TARGET_OPENRISC) || defined(TARGET_TILEGX)
/* These are the asm-generic versions of the stat and stat64 structures */
@@ -2264,7 +2266,9 @@ struct target_flock {
struct target_flock64 {
short l_type;
short l_whence;
-#if defined(TARGET_PPC) || defined(TARGET_X86_64) || defined(TARGET_MIPS) || defined(TARGET_SPARC) || defined(TARGET_HPPA) || defined (TARGET_MICROBLAZE)
+#if defined(TARGET_PPC) || defined(TARGET_X86_64) || defined(TARGET_MIPS) \
+ || defined(TARGET_SPARC) || defined(TARGET_HPPA) \
+ || defined(TARGET_MICROBLAZE) || defined(TARGET_TILEGX)
int __pad;
#endif
unsigned long long l_start;
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 03/33] linux-user: Conditionalize syscalls which are not defined in tilegx
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 01/33] linux-user: tilegx: Firstly add architecture related features Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 02/33] linux-user: Support tilegx architecture in linux-user Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 04/33] target-tilegx: Add opcode basic implementation from Tilera Corporation Richard Henderson
` (29 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, Chen Gang, xili_gchen_5257, peter.maydell
From: Chen Gang <xili_gchen_5257@hotmail.com>
Some of architectures (e.g. tilegx), several syscall macros are not
supported, so switch them.
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <BLU436-SMTP457D6FC9B2B9BA87AEB22CB9660@phx.gbl>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
linux-user/syscall.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index f62c698..64e28f8 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -213,7 +213,7 @@ static int gettid(void) {
return -ENOSYS;
}
#endif
-#ifdef __NR_getdents
+#if defined(TARGET_NR_getdents) && defined(__NR_getdents)
_syscall3(int, sys_getdents, uint, fd, struct linux_dirent *, dirp, uint, count);
#endif
#if !defined(__NR_getdents) || \
@@ -5639,6 +5639,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(write(arg1, p, arg3));
unlock_user(p, arg2, 0);
break;
+#ifdef TARGET_NR_open
case TARGET_NR_open:
if (!(p = lock_user_string(arg1)))
goto efault;
@@ -5647,6 +5648,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
arg3));
unlock_user(p, arg1, 0);
break;
+#endif
case TARGET_NR_openat:
if (!(p = lock_user_string(arg2)))
goto efault;
@@ -5661,9 +5663,11 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
case TARGET_NR_brk:
ret = do_brk(arg1);
break;
+#ifdef TARGET_NR_fork
case TARGET_NR_fork:
ret = get_errno(do_fork(cpu_env, SIGCHLD, 0, 0, 0, 0));
break;
+#endif
#ifdef TARGET_NR_waitpid
case TARGET_NR_waitpid:
{
@@ -5698,6 +5702,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
break;
#endif
+#ifdef TARGET_NR_link
case TARGET_NR_link:
{
void * p2;
@@ -5711,6 +5716,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_linkat)
case TARGET_NR_linkat:
{
@@ -5728,12 +5734,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
+#ifdef TARGET_NR_unlink
case TARGET_NR_unlink:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(unlink(p));
unlock_user(p, arg1, 0);
break;
+#endif
#if defined(TARGET_NR_unlinkat)
case TARGET_NR_unlinkat:
if (!(p = lock_user_string(arg2)))
@@ -5850,12 +5858,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
+#ifdef TARGET_NR_mknod
case TARGET_NR_mknod:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(mknod(p, arg2, arg3));
unlock_user(p, arg1, 0);
break;
+#endif
#if defined(TARGET_NR_mknodat)
case TARGET_NR_mknodat:
if (!(p = lock_user_string(arg2)))
@@ -5864,12 +5874,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg2, 0);
break;
#endif
+#ifdef TARGET_NR_chmod
case TARGET_NR_chmod:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(chmod(p, arg2));
unlock_user(p, arg1, 0);
break;
+#endif
#ifdef TARGET_NR_break
case TARGET_NR_break:
goto unimplemented;
@@ -6004,6 +6016,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
+#ifdef TARGET_NR_utimes
case TARGET_NR_utimes:
{
struct timeval *tvp, tv[2];
@@ -6022,6 +6035,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_futimesat)
case TARGET_NR_futimesat:
{
@@ -6050,12 +6064,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
case TARGET_NR_gtty:
goto unimplemented;
#endif
+#ifdef TARGET_NR_access
case TARGET_NR_access:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(access(path(p), arg2));
unlock_user(p, arg1, 0);
break;
+#endif
#if defined(TARGET_NR_faccessat) && defined(__NR_faccessat)
case TARGET_NR_faccessat:
if (!(p = lock_user_string(arg2)))
@@ -6080,6 +6096,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
case TARGET_NR_kill:
ret = get_errno(kill(arg1, target_to_host_signal(arg2)));
break;
+#ifdef TARGET_NR_rename
case TARGET_NR_rename:
{
void *p2;
@@ -6093,6 +6110,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_renameat)
case TARGET_NR_renameat:
{
@@ -6108,12 +6126,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
+#ifdef TARGET_NR_mkdir
case TARGET_NR_mkdir:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(mkdir(p, arg2));
unlock_user(p, arg1, 0);
break;
+#endif
#if defined(TARGET_NR_mkdirat)
case TARGET_NR_mkdirat:
if (!(p = lock_user_string(arg2)))
@@ -6122,18 +6142,22 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg2, 0);
break;
#endif
+#ifdef TARGET_NR_rmdir
case TARGET_NR_rmdir:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(rmdir(p));
unlock_user(p, arg1, 0);
break;
+#endif
case TARGET_NR_dup:
ret = get_errno(dup(arg1));
break;
+#ifdef TARGET_NR_pipe
case TARGET_NR_pipe:
ret = do_pipe(cpu_env, arg1, 0, 0);
break;
+#endif
#ifdef TARGET_NR_pipe2
case TARGET_NR_pipe2:
ret = do_pipe(cpu_env, arg1,
@@ -6218,11 +6242,15 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(chroot(p));
unlock_user(p, arg1, 0);
break;
+#ifdef TARGET_NR_ustat
case TARGET_NR_ustat:
goto unimplemented;
+#endif
+#ifdef TARGET_NR_dup2
case TARGET_NR_dup2:
ret = get_errno(dup2(arg1, arg2));
break;
+#endif
#if defined(CONFIG_DUP3) && defined(TARGET_NR_dup3)
case TARGET_NR_dup3:
ret = get_errno(dup3(arg1, arg2, arg3));
@@ -6233,9 +6261,11 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(getppid());
break;
#endif
+#ifdef TARGET_NR_getpgrp
case TARGET_NR_getpgrp:
ret = get_errno(getpgrp());
break;
+#endif
case TARGET_NR_setsid:
ret = get_errno(setsid());
break;
@@ -6811,6 +6841,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
+#ifdef TARGET_NR_symlink
case TARGET_NR_symlink:
{
void *p2;
@@ -6824,6 +6855,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_symlinkat)
case TARGET_NR_symlinkat:
{
@@ -6843,6 +6875,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
case TARGET_NR_oldlstat:
goto unimplemented;
#endif
+#ifdef TARGET_NR_readlink
case TARGET_NR_readlink:
{
void *p2;
@@ -6873,6 +6906,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_readlinkat)
case TARGET_NR_readlinkat:
{
@@ -7272,22 +7306,28 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
}
break;
+#ifdef TARGET_NR_stat
case TARGET_NR_stat:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(stat(path(p), &st));
unlock_user(p, arg1, 0);
goto do_stat;
+#endif
+#ifdef TARGET_NR_lstat
case TARGET_NR_lstat:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(lstat(path(p), &st));
unlock_user(p, arg1, 0);
goto do_stat;
+#endif
case TARGET_NR_fstat:
{
ret = get_errno(fstat(arg1, &st));
+#if defined(TARGET_NR_stat) || defined(TARGET_NR_lstat)
do_stat:
+#endif
if (!is_error(ret)) {
struct target_stat *target_st;
@@ -7575,6 +7615,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
+#ifdef TARGET_NR_getdents
case TARGET_NR_getdents:
#ifdef __NR_getdents
#if TARGET_ABI_BITS == 32 && HOST_LONG_BITS == 64
@@ -7705,6 +7746,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
#endif
break;
+#endif /* TARGET_NR_getdents */
#if defined(TARGET_NR_getdents64) && defined(__NR_getdents64)
case TARGET_NR_getdents64:
{
@@ -7844,11 +7886,13 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(fdatasync(arg1));
break;
#endif
+#ifdef TARGET_NR__sysctl
case TARGET_NR__sysctl:
/* We don't implement this, but ENOTDIR is always a safe
return value. */
ret = -TARGET_ENOTDIR;
break;
+#endif
case TARGET_NR_sched_getaffinity:
{
unsigned int mask_size;
@@ -8295,12 +8339,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = host_to_target_stat64(cpu_env, arg3, &st);
break;
#endif
+#ifdef TARGET_NR_lchown
case TARGET_NR_lchown:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(lchown(p, low2highuid(arg2), low2highgid(arg3)));
unlock_user(p, arg1, 0);
break;
+#endif
#ifdef TARGET_NR_getuid
case TARGET_NR_getuid:
ret = get_errno(high2lowuid(getuid()));
@@ -8423,12 +8469,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
+#ifdef TARGET_NR_chown
case TARGET_NR_chown:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(chown(p, low2highuid(arg2), low2highgid(arg3)));
unlock_user(p, arg1, 0);
break;
+#endif
case TARGET_NR_setuid:
ret = get_errno(setuid(low2highuid(arg1)));
break;
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 04/33] target-tilegx: Add opcode basic implementation from Tilera Corporation
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (2 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 03/33] linux-user: Conditionalize syscalls which are not defined in tilegx Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 05/33] target-tilegx: Modify opcode_tilegx.h to fit QEMU usage Richard Henderson
` (28 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, Chen Gang, xili_gchen_5257, peter.maydell
From: Chen Gang <xili_gchen_5257@hotmail.com>
It is copied from Linux kernel "arch/tile/include/uapi/arch/
opcode_tilegx.h".
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <BLU436-SMTP2087FA98B64A20B25155D9AB9660@phx.gbl>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/opcode_tilegx.h | 1406 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 1406 insertions(+)
create mode 100644 target-tilegx/opcode_tilegx.h
diff --git a/target-tilegx/opcode_tilegx.h b/target-tilegx/opcode_tilegx.h
new file mode 100644
index 0000000..d76ff2d
--- /dev/null
+++ b/target-tilegx/opcode_tilegx.h
@@ -0,0 +1,1406 @@
+/* TILE-Gx opcode information.
+ *
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ *
+ *
+ *
+ *
+ *
+ */
+
+#ifndef __ARCH_OPCODE_H__
+#define __ARCH_OPCODE_H__
+
+#ifndef __ASSEMBLER__
+
+typedef unsigned long long tilegx_bundle_bits;
+
+/* These are the bits that determine if a bundle is in the X encoding. */
+#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
+
+enum
+{
+ /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
+ TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
+
+ /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
+ TILEGX_NUM_PIPELINE_ENCODINGS = 5,
+
+ /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
+ TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
+
+ /* Instructions take this many bytes. */
+ TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
+
+ /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
+ TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
+
+ /* Bundles should be aligned modulo this number of bytes. */
+ TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
+ (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
+
+ /* Number of registers (some are magic, such as network I/O). */
+ TILEGX_NUM_REGISTERS = 64,
+};
+
+/* Make a few "tile_" variables to simplify common code between
+ architectures. */
+
+typedef tilegx_bundle_bits tile_bundle_bits;
+#define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES
+#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
+#define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \
+ TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES
+#define TILE_BPT_BUNDLE TILEGX_BPT_BUNDLE
+
+/* 64-bit pattern for a { bpt ; nop } bundle. */
+#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
+
+static __inline unsigned int
+get_BFEnd_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 12)) & 0x3f);
+}
+
+static __inline unsigned int
+get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 24)) & 0xf);
+}
+
+static __inline unsigned int
+get_BFStart_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 18)) & 0x3f);
+}
+
+static __inline unsigned int
+get_BrOff_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 31)) & 0x0000003f) |
+ (((unsigned int)(n >> 37)) & 0x0001ffc0);
+}
+
+static __inline unsigned int
+get_BrType_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 54)) & 0x1f);
+}
+
+static __inline unsigned int
+get_Dest_Imm8_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 31)) & 0x0000003f) |
+ (((unsigned int)(n >> 43)) & 0x000000c0);
+}
+
+static __inline unsigned int
+get_Dest_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 0)) & 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 31)) & 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_Y0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 0)) & 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_Y1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 31)) & 0x3f);
+}
+
+static __inline unsigned int
+get_Imm16_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 12)) & 0xffff);
+}
+
+static __inline unsigned int
+get_Imm16_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 43)) & 0xffff);
+}
+
+static __inline unsigned int
+get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 20)) & 0xff);
+}
+
+static __inline unsigned int
+get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 51)) & 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 12)) & 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 43)) & 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_Y0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 12)) & 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_Y1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 43)) & 0xff);
+}
+
+static __inline unsigned int
+get_JumpOff_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 31)) & 0x7ffffff);
+}
+
+static __inline unsigned int
+get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 58)) & 0x1);
+}
+
+static __inline unsigned int
+get_MF_Imm14_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 37)) & 0x3fff);
+}
+
+static __inline unsigned int
+get_MT_Imm14_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 31)) & 0x0000003f) |
+ (((unsigned int)(n >> 37)) & 0x00003fc0);
+}
+
+static __inline unsigned int
+get_Mode(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 62)) & 0x3);
+}
+
+static __inline unsigned int
+get_Opcode_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 28)) & 0x7);
+}
+
+static __inline unsigned int
+get_Opcode_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 59)) & 0x7);
+}
+
+static __inline unsigned int
+get_Opcode_Y0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 27)) & 0xf);
+}
+
+static __inline unsigned int
+get_Opcode_Y1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 58)) & 0xf);
+}
+
+static __inline unsigned int
+get_Opcode_Y2(tilegx_bundle_bits n)
+{
+ return (((n >> 26)) & 0x00000001) |
+ (((unsigned int)(n >> 56)) & 0x00000002);
+}
+
+static __inline unsigned int
+get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 18)) & 0x3ff);
+}
+
+static __inline unsigned int
+get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 49)) & 0x3ff);
+}
+
+static __inline unsigned int
+get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 18)) & 0x3);
+}
+
+static __inline unsigned int
+get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 49)) & 0x3);
+}
+
+static __inline unsigned int
+get_ShAmt_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 12)) & 0x3f);
+}
+
+static __inline unsigned int
+get_ShAmt_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 43)) & 0x3f);
+}
+
+static __inline unsigned int
+get_ShAmt_Y0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 12)) & 0x3f);
+}
+
+static __inline unsigned int
+get_ShAmt_Y1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 43)) & 0x3f);
+}
+
+static __inline unsigned int
+get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 18)) & 0x3ff);
+}
+
+static __inline unsigned int
+get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 49)) & 0x3ff);
+}
+
+static __inline unsigned int
+get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 18)) & 0x3);
+}
+
+static __inline unsigned int
+get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 49)) & 0x3);
+}
+
+static __inline unsigned int
+get_SrcA_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 6)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcA_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 37)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcA_Y0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 6)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcA_Y1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 37)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcA_Y2(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 20)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcBDest_Y2(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 51)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcB_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 12)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcB_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 43)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcB_Y0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 12)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcB_Y1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 43)) & 0x3f);
+}
+
+static __inline unsigned int
+get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 12)) & 0x3f);
+}
+
+static __inline unsigned int
+get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 43)) & 0x3f);
+}
+
+static __inline unsigned int
+get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 12)) & 0x3f);
+}
+
+static __inline unsigned int
+get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 43)) & 0x3f);
+}
+
+
+static __inline int
+sign_extend(int n, int num_bits)
+{
+ int shift = (int)(sizeof(int) * 8 - num_bits);
+ return (n << shift) >> shift;
+}
+
+
+
+static __inline tilegx_bundle_bits
+create_BFEnd_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3f) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_BFOpcodeExtension_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0xf) << 24);
+}
+
+static __inline tilegx_bundle_bits
+create_BFStart_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3f) << 18);
+}
+
+static __inline tilegx_bundle_bits
+create_BrOff_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
+ (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
+}
+
+static __inline tilegx_bundle_bits
+create_BrType_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
+}
+
+static __inline tilegx_bundle_bits
+create_Dest_Imm8_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
+ (((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_Dest_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3f) << 0);
+}
+
+static __inline tilegx_bundle_bits
+create_Dest_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
+}
+
+static __inline tilegx_bundle_bits
+create_Dest_Y0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3f) << 0);
+}
+
+static __inline tilegx_bundle_bits
+create_Dest_Y1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
+}
+
+static __inline tilegx_bundle_bits
+create_Imm16_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0xffff) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_Imm16_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_Imm8OpcodeExtension_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0xff) << 20);
+}
+
+static __inline tilegx_bundle_bits
+create_Imm8OpcodeExtension_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0xff)) << 51);
+}
+
+static __inline tilegx_bundle_bits
+create_Imm8_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0xff) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_Imm8_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0xff)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_Imm8_Y0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0xff) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_Imm8_Y1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0xff)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_JumpOff_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
+}
+
+static __inline tilegx_bundle_bits
+create_JumpOpcodeExtension_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x1)) << 58);
+}
+
+static __inline tilegx_bundle_bits
+create_MF_Imm14_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
+}
+
+static __inline tilegx_bundle_bits
+create_MT_Imm14_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
+ (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
+}
+
+static __inline tilegx_bundle_bits
+create_Mode(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3)) << 62);
+}
+
+static __inline tilegx_bundle_bits
+create_Opcode_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x7) << 28);
+}
+
+static __inline tilegx_bundle_bits
+create_Opcode_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x7)) << 59);
+}
+
+static __inline tilegx_bundle_bits
+create_Opcode_Y0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0xf) << 27);
+}
+
+static __inline tilegx_bundle_bits
+create_Opcode_Y1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0xf)) << 58);
+}
+
+static __inline tilegx_bundle_bits
+create_Opcode_Y2(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x00000001) << 26) |
+ (((tilegx_bundle_bits)(n & 0x00000002)) << 56);
+}
+
+static __inline tilegx_bundle_bits
+create_RRROpcodeExtension_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3ff) << 18);
+}
+
+static __inline tilegx_bundle_bits
+create_RRROpcodeExtension_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
+}
+
+static __inline tilegx_bundle_bits
+create_RRROpcodeExtension_Y0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3) << 18);
+}
+
+static __inline tilegx_bundle_bits
+create_RRROpcodeExtension_Y1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3)) << 49);
+}
+
+static __inline tilegx_bundle_bits
+create_ShAmt_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3f) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_ShAmt_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_ShAmt_Y0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3f) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_ShAmt_Y1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_ShiftOpcodeExtension_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3ff) << 18);
+}
+
+static __inline tilegx_bundle_bits
+create_ShiftOpcodeExtension_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
+}
+
+static __inline tilegx_bundle_bits
+create_ShiftOpcodeExtension_Y0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3) << 18);
+}
+
+static __inline tilegx_bundle_bits
+create_ShiftOpcodeExtension_Y1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3)) << 49);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcA_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3f) << 6);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcA_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcA_Y0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3f) << 6);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcA_Y1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcA_Y2(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3f) << 20);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcBDest_Y2(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcB_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3f) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcB_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcB_Y0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3f) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_SrcB_Y1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_UnaryOpcodeExtension_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3f) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_UnaryOpcodeExtension_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
+}
+
+static __inline tilegx_bundle_bits
+create_UnaryOpcodeExtension_Y0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3f) << 12);
+}
+
+static __inline tilegx_bundle_bits
+create_UnaryOpcodeExtension_Y1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
+}
+
+
+enum
+{
+ ADDI_IMM8_OPCODE_X0 = 1,
+ ADDI_IMM8_OPCODE_X1 = 1,
+ ADDI_OPCODE_Y0 = 0,
+ ADDI_OPCODE_Y1 = 1,
+ ADDLI_OPCODE_X0 = 1,
+ ADDLI_OPCODE_X1 = 0,
+ ADDXI_IMM8_OPCODE_X0 = 2,
+ ADDXI_IMM8_OPCODE_X1 = 2,
+ ADDXI_OPCODE_Y0 = 1,
+ ADDXI_OPCODE_Y1 = 2,
+ ADDXLI_OPCODE_X0 = 2,
+ ADDXLI_OPCODE_X1 = 1,
+ ADDXSC_RRR_0_OPCODE_X0 = 1,
+ ADDXSC_RRR_0_OPCODE_X1 = 1,
+ ADDX_RRR_0_OPCODE_X0 = 2,
+ ADDX_RRR_0_OPCODE_X1 = 2,
+ ADDX_RRR_0_OPCODE_Y0 = 0,
+ ADDX_SPECIAL_0_OPCODE_Y1 = 0,
+ ADD_RRR_0_OPCODE_X0 = 3,
+ ADD_RRR_0_OPCODE_X1 = 3,
+ ADD_RRR_0_OPCODE_Y0 = 1,
+ ADD_SPECIAL_0_OPCODE_Y1 = 1,
+ ANDI_IMM8_OPCODE_X0 = 3,
+ ANDI_IMM8_OPCODE_X1 = 3,
+ ANDI_OPCODE_Y0 = 2,
+ ANDI_OPCODE_Y1 = 3,
+ AND_RRR_0_OPCODE_X0 = 4,
+ AND_RRR_0_OPCODE_X1 = 4,
+ AND_RRR_5_OPCODE_Y0 = 0,
+ AND_RRR_5_OPCODE_Y1 = 0,
+ BEQZT_BRANCH_OPCODE_X1 = 16,
+ BEQZ_BRANCH_OPCODE_X1 = 17,
+ BFEXTS_BF_OPCODE_X0 = 4,
+ BFEXTU_BF_OPCODE_X0 = 5,
+ BFINS_BF_OPCODE_X0 = 6,
+ BF_OPCODE_X0 = 3,
+ BGEZT_BRANCH_OPCODE_X1 = 18,
+ BGEZ_BRANCH_OPCODE_X1 = 19,
+ BGTZT_BRANCH_OPCODE_X1 = 20,
+ BGTZ_BRANCH_OPCODE_X1 = 21,
+ BLBCT_BRANCH_OPCODE_X1 = 22,
+ BLBC_BRANCH_OPCODE_X1 = 23,
+ BLBST_BRANCH_OPCODE_X1 = 24,
+ BLBS_BRANCH_OPCODE_X1 = 25,
+ BLEZT_BRANCH_OPCODE_X1 = 26,
+ BLEZ_BRANCH_OPCODE_X1 = 27,
+ BLTZT_BRANCH_OPCODE_X1 = 28,
+ BLTZ_BRANCH_OPCODE_X1 = 29,
+ BNEZT_BRANCH_OPCODE_X1 = 30,
+ BNEZ_BRANCH_OPCODE_X1 = 31,
+ BRANCH_OPCODE_X1 = 2,
+ CMOVEQZ_RRR_0_OPCODE_X0 = 5,
+ CMOVEQZ_RRR_4_OPCODE_Y0 = 0,
+ CMOVNEZ_RRR_0_OPCODE_X0 = 6,
+ CMOVNEZ_RRR_4_OPCODE_Y0 = 1,
+ CMPEQI_IMM8_OPCODE_X0 = 4,
+ CMPEQI_IMM8_OPCODE_X1 = 4,
+ CMPEQI_OPCODE_Y0 = 3,
+ CMPEQI_OPCODE_Y1 = 4,
+ CMPEQ_RRR_0_OPCODE_X0 = 7,
+ CMPEQ_RRR_0_OPCODE_X1 = 5,
+ CMPEQ_RRR_3_OPCODE_Y0 = 0,
+ CMPEQ_RRR_3_OPCODE_Y1 = 2,
+ CMPEXCH4_RRR_0_OPCODE_X1 = 6,
+ CMPEXCH_RRR_0_OPCODE_X1 = 7,
+ CMPLES_RRR_0_OPCODE_X0 = 8,
+ CMPLES_RRR_0_OPCODE_X1 = 8,
+ CMPLES_RRR_2_OPCODE_Y0 = 0,
+ CMPLES_RRR_2_OPCODE_Y1 = 0,
+ CMPLEU_RRR_0_OPCODE_X0 = 9,
+ CMPLEU_RRR_0_OPCODE_X1 = 9,
+ CMPLEU_RRR_2_OPCODE_Y0 = 1,
+ CMPLEU_RRR_2_OPCODE_Y1 = 1,
+ CMPLTSI_IMM8_OPCODE_X0 = 5,
+ CMPLTSI_IMM8_OPCODE_X1 = 5,
+ CMPLTSI_OPCODE_Y0 = 4,
+ CMPLTSI_OPCODE_Y1 = 5,
+ CMPLTS_RRR_0_OPCODE_X0 = 10,
+ CMPLTS_RRR_0_OPCODE_X1 = 10,
+ CMPLTS_RRR_2_OPCODE_Y0 = 2,
+ CMPLTS_RRR_2_OPCODE_Y1 = 2,
+ CMPLTUI_IMM8_OPCODE_X0 = 6,
+ CMPLTUI_IMM8_OPCODE_X1 = 6,
+ CMPLTU_RRR_0_OPCODE_X0 = 11,
+ CMPLTU_RRR_0_OPCODE_X1 = 11,
+ CMPLTU_RRR_2_OPCODE_Y0 = 3,
+ CMPLTU_RRR_2_OPCODE_Y1 = 3,
+ CMPNE_RRR_0_OPCODE_X0 = 12,
+ CMPNE_RRR_0_OPCODE_X1 = 12,
+ CMPNE_RRR_3_OPCODE_Y0 = 1,
+ CMPNE_RRR_3_OPCODE_Y1 = 3,
+ CMULAF_RRR_0_OPCODE_X0 = 13,
+ CMULA_RRR_0_OPCODE_X0 = 14,
+ CMULFR_RRR_0_OPCODE_X0 = 15,
+ CMULF_RRR_0_OPCODE_X0 = 16,
+ CMULHR_RRR_0_OPCODE_X0 = 17,
+ CMULH_RRR_0_OPCODE_X0 = 18,
+ CMUL_RRR_0_OPCODE_X0 = 19,
+ CNTLZ_UNARY_OPCODE_X0 = 1,
+ CNTLZ_UNARY_OPCODE_Y0 = 1,
+ CNTTZ_UNARY_OPCODE_X0 = 2,
+ CNTTZ_UNARY_OPCODE_Y0 = 2,
+ CRC32_32_RRR_0_OPCODE_X0 = 20,
+ CRC32_8_RRR_0_OPCODE_X0 = 21,
+ DBLALIGN2_RRR_0_OPCODE_X0 = 22,
+ DBLALIGN2_RRR_0_OPCODE_X1 = 13,
+ DBLALIGN4_RRR_0_OPCODE_X0 = 23,
+ DBLALIGN4_RRR_0_OPCODE_X1 = 14,
+ DBLALIGN6_RRR_0_OPCODE_X0 = 24,
+ DBLALIGN6_RRR_0_OPCODE_X1 = 15,
+ DBLALIGN_RRR_0_OPCODE_X0 = 25,
+ DRAIN_UNARY_OPCODE_X1 = 1,
+ DTLBPR_UNARY_OPCODE_X1 = 2,
+ EXCH4_RRR_0_OPCODE_X1 = 16,
+ EXCH_RRR_0_OPCODE_X1 = 17,
+ FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26,
+ FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27,
+ FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28,
+ FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29,
+ FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30,
+ FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31,
+ FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32,
+ FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33,
+ FETCHADD4_RRR_0_OPCODE_X1 = 18,
+ FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19,
+ FETCHADDGEZ_RRR_0_OPCODE_X1 = 20,
+ FETCHADD_RRR_0_OPCODE_X1 = 21,
+ FETCHAND4_RRR_0_OPCODE_X1 = 22,
+ FETCHAND_RRR_0_OPCODE_X1 = 23,
+ FETCHOR4_RRR_0_OPCODE_X1 = 24,
+ FETCHOR_RRR_0_OPCODE_X1 = 25,
+ FINV_UNARY_OPCODE_X1 = 3,
+ FLUSHWB_UNARY_OPCODE_X1 = 4,
+ FLUSH_UNARY_OPCODE_X1 = 5,
+ FNOP_UNARY_OPCODE_X0 = 3,
+ FNOP_UNARY_OPCODE_X1 = 6,
+ FNOP_UNARY_OPCODE_Y0 = 3,
+ FNOP_UNARY_OPCODE_Y1 = 8,
+ FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34,
+ FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35,
+ FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36,
+ FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37,
+ FSINGLE_PACK1_UNARY_OPCODE_X0 = 4,
+ FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4,
+ FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38,
+ FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39,
+ ICOH_UNARY_OPCODE_X1 = 7,
+ ILL_UNARY_OPCODE_X1 = 8,
+ ILL_UNARY_OPCODE_Y1 = 9,
+ IMM8_OPCODE_X0 = 4,
+ IMM8_OPCODE_X1 = 3,
+ INV_UNARY_OPCODE_X1 = 9,
+ IRET_UNARY_OPCODE_X1 = 10,
+ JALRP_UNARY_OPCODE_X1 = 11,
+ JALRP_UNARY_OPCODE_Y1 = 10,
+ JALR_UNARY_OPCODE_X1 = 12,
+ JALR_UNARY_OPCODE_Y1 = 11,
+ JAL_JUMP_OPCODE_X1 = 0,
+ JRP_UNARY_OPCODE_X1 = 13,
+ JRP_UNARY_OPCODE_Y1 = 12,
+ JR_UNARY_OPCODE_X1 = 14,
+ JR_UNARY_OPCODE_Y1 = 13,
+ JUMP_OPCODE_X1 = 4,
+ J_JUMP_OPCODE_X1 = 1,
+ LD1S_ADD_IMM8_OPCODE_X1 = 7,
+ LD1S_OPCODE_Y2 = 0,
+ LD1S_UNARY_OPCODE_X1 = 15,
+ LD1U_ADD_IMM8_OPCODE_X1 = 8,
+ LD1U_OPCODE_Y2 = 1,
+ LD1U_UNARY_OPCODE_X1 = 16,
+ LD2S_ADD_IMM8_OPCODE_X1 = 9,
+ LD2S_OPCODE_Y2 = 2,
+ LD2S_UNARY_OPCODE_X1 = 17,
+ LD2U_ADD_IMM8_OPCODE_X1 = 10,
+ LD2U_OPCODE_Y2 = 3,
+ LD2U_UNARY_OPCODE_X1 = 18,
+ LD4S_ADD_IMM8_OPCODE_X1 = 11,
+ LD4S_OPCODE_Y2 = 1,
+ LD4S_UNARY_OPCODE_X1 = 19,
+ LD4U_ADD_IMM8_OPCODE_X1 = 12,
+ LD4U_OPCODE_Y2 = 2,
+ LD4U_UNARY_OPCODE_X1 = 20,
+ LDNA_UNARY_OPCODE_X1 = 21,
+ LDNT1S_ADD_IMM8_OPCODE_X1 = 13,
+ LDNT1S_UNARY_OPCODE_X1 = 22,
+ LDNT1U_ADD_IMM8_OPCODE_X1 = 14,
+ LDNT1U_UNARY_OPCODE_X1 = 23,
+ LDNT2S_ADD_IMM8_OPCODE_X1 = 15,
+ LDNT2S_UNARY_OPCODE_X1 = 24,
+ LDNT2U_ADD_IMM8_OPCODE_X1 = 16,
+ LDNT2U_UNARY_OPCODE_X1 = 25,
+ LDNT4S_ADD_IMM8_OPCODE_X1 = 17,
+ LDNT4S_UNARY_OPCODE_X1 = 26,
+ LDNT4U_ADD_IMM8_OPCODE_X1 = 18,
+ LDNT4U_UNARY_OPCODE_X1 = 27,
+ LDNT_ADD_IMM8_OPCODE_X1 = 19,
+ LDNT_UNARY_OPCODE_X1 = 28,
+ LD_ADD_IMM8_OPCODE_X1 = 20,
+ LD_OPCODE_Y2 = 3,
+ LD_UNARY_OPCODE_X1 = 29,
+ LNK_UNARY_OPCODE_X1 = 30,
+ LNK_UNARY_OPCODE_Y1 = 14,
+ LWNA_ADD_IMM8_OPCODE_X1 = 21,
+ MFSPR_IMM8_OPCODE_X1 = 22,
+ MF_UNARY_OPCODE_X1 = 31,
+ MM_BF_OPCODE_X0 = 7,
+ MNZ_RRR_0_OPCODE_X0 = 40,
+ MNZ_RRR_0_OPCODE_X1 = 26,
+ MNZ_RRR_4_OPCODE_Y0 = 2,
+ MNZ_RRR_4_OPCODE_Y1 = 2,
+ MODE_OPCODE_YA2 = 1,
+ MODE_OPCODE_YB2 = 2,
+ MODE_OPCODE_YC2 = 3,
+ MTSPR_IMM8_OPCODE_X1 = 23,
+ MULAX_RRR_0_OPCODE_X0 = 41,
+ MULAX_RRR_3_OPCODE_Y0 = 2,
+ MULA_HS_HS_RRR_0_OPCODE_X0 = 42,
+ MULA_HS_HS_RRR_9_OPCODE_Y0 = 0,
+ MULA_HS_HU_RRR_0_OPCODE_X0 = 43,
+ MULA_HS_LS_RRR_0_OPCODE_X0 = 44,
+ MULA_HS_LU_RRR_0_OPCODE_X0 = 45,
+ MULA_HU_HU_RRR_0_OPCODE_X0 = 46,
+ MULA_HU_HU_RRR_9_OPCODE_Y0 = 1,
+ MULA_HU_LS_RRR_0_OPCODE_X0 = 47,
+ MULA_HU_LU_RRR_0_OPCODE_X0 = 48,
+ MULA_LS_LS_RRR_0_OPCODE_X0 = 49,
+ MULA_LS_LS_RRR_9_OPCODE_Y0 = 2,
+ MULA_LS_LU_RRR_0_OPCODE_X0 = 50,
+ MULA_LU_LU_RRR_0_OPCODE_X0 = 51,
+ MULA_LU_LU_RRR_9_OPCODE_Y0 = 3,
+ MULX_RRR_0_OPCODE_X0 = 52,
+ MULX_RRR_3_OPCODE_Y0 = 3,
+ MUL_HS_HS_RRR_0_OPCODE_X0 = 53,
+ MUL_HS_HS_RRR_8_OPCODE_Y0 = 0,
+ MUL_HS_HU_RRR_0_OPCODE_X0 = 54,
+ MUL_HS_LS_RRR_0_OPCODE_X0 = 55,
+ MUL_HS_LU_RRR_0_OPCODE_X0 = 56,
+ MUL_HU_HU_RRR_0_OPCODE_X0 = 57,
+ MUL_HU_HU_RRR_8_OPCODE_Y0 = 1,
+ MUL_HU_LS_RRR_0_OPCODE_X0 = 58,
+ MUL_HU_LU_RRR_0_OPCODE_X0 = 59,
+ MUL_LS_LS_RRR_0_OPCODE_X0 = 60,
+ MUL_LS_LS_RRR_8_OPCODE_Y0 = 2,
+ MUL_LS_LU_RRR_0_OPCODE_X0 = 61,
+ MUL_LU_LU_RRR_0_OPCODE_X0 = 62,
+ MUL_LU_LU_RRR_8_OPCODE_Y0 = 3,
+ MZ_RRR_0_OPCODE_X0 = 63,
+ MZ_RRR_0_OPCODE_X1 = 27,
+ MZ_RRR_4_OPCODE_Y0 = 3,
+ MZ_RRR_4_OPCODE_Y1 = 3,
+ NAP_UNARY_OPCODE_X1 = 32,
+ NOP_UNARY_OPCODE_X0 = 5,
+ NOP_UNARY_OPCODE_X1 = 33,
+ NOP_UNARY_OPCODE_Y0 = 5,
+ NOP_UNARY_OPCODE_Y1 = 15,
+ NOR_RRR_0_OPCODE_X0 = 64,
+ NOR_RRR_0_OPCODE_X1 = 28,
+ NOR_RRR_5_OPCODE_Y0 = 1,
+ NOR_RRR_5_OPCODE_Y1 = 1,
+ ORI_IMM8_OPCODE_X0 = 7,
+ ORI_IMM8_OPCODE_X1 = 24,
+ OR_RRR_0_OPCODE_X0 = 65,
+ OR_RRR_0_OPCODE_X1 = 29,
+ OR_RRR_5_OPCODE_Y0 = 2,
+ OR_RRR_5_OPCODE_Y1 = 2,
+ PCNT_UNARY_OPCODE_X0 = 6,
+ PCNT_UNARY_OPCODE_Y0 = 6,
+ REVBITS_UNARY_OPCODE_X0 = 7,
+ REVBITS_UNARY_OPCODE_Y0 = 7,
+ REVBYTES_UNARY_OPCODE_X0 = 8,
+ REVBYTES_UNARY_OPCODE_Y0 = 8,
+ ROTLI_SHIFT_OPCODE_X0 = 1,
+ ROTLI_SHIFT_OPCODE_X1 = 1,
+ ROTLI_SHIFT_OPCODE_Y0 = 0,
+ ROTLI_SHIFT_OPCODE_Y1 = 0,
+ ROTL_RRR_0_OPCODE_X0 = 66,
+ ROTL_RRR_0_OPCODE_X1 = 30,
+ ROTL_RRR_6_OPCODE_Y0 = 0,
+ ROTL_RRR_6_OPCODE_Y1 = 0,
+ RRR_0_OPCODE_X0 = 5,
+ RRR_0_OPCODE_X1 = 5,
+ RRR_0_OPCODE_Y0 = 5,
+ RRR_0_OPCODE_Y1 = 6,
+ RRR_1_OPCODE_Y0 = 6,
+ RRR_1_OPCODE_Y1 = 7,
+ RRR_2_OPCODE_Y0 = 7,
+ RRR_2_OPCODE_Y1 = 8,
+ RRR_3_OPCODE_Y0 = 8,
+ RRR_3_OPCODE_Y1 = 9,
+ RRR_4_OPCODE_Y0 = 9,
+ RRR_4_OPCODE_Y1 = 10,
+ RRR_5_OPCODE_Y0 = 10,
+ RRR_5_OPCODE_Y1 = 11,
+ RRR_6_OPCODE_Y0 = 11,
+ RRR_6_OPCODE_Y1 = 12,
+ RRR_7_OPCODE_Y0 = 12,
+ RRR_7_OPCODE_Y1 = 13,
+ RRR_8_OPCODE_Y0 = 13,
+ RRR_9_OPCODE_Y0 = 14,
+ SHIFT_OPCODE_X0 = 6,
+ SHIFT_OPCODE_X1 = 6,
+ SHIFT_OPCODE_Y0 = 15,
+ SHIFT_OPCODE_Y1 = 14,
+ SHL16INSLI_OPCODE_X0 = 7,
+ SHL16INSLI_OPCODE_X1 = 7,
+ SHL1ADDX_RRR_0_OPCODE_X0 = 67,
+ SHL1ADDX_RRR_0_OPCODE_X1 = 31,
+ SHL1ADDX_RRR_7_OPCODE_Y0 = 1,
+ SHL1ADDX_RRR_7_OPCODE_Y1 = 1,
+ SHL1ADD_RRR_0_OPCODE_X0 = 68,
+ SHL1ADD_RRR_0_OPCODE_X1 = 32,
+ SHL1ADD_RRR_1_OPCODE_Y0 = 0,
+ SHL1ADD_RRR_1_OPCODE_Y1 = 0,
+ SHL2ADDX_RRR_0_OPCODE_X0 = 69,
+ SHL2ADDX_RRR_0_OPCODE_X1 = 33,
+ SHL2ADDX_RRR_7_OPCODE_Y0 = 2,
+ SHL2ADDX_RRR_7_OPCODE_Y1 = 2,
+ SHL2ADD_RRR_0_OPCODE_X0 = 70,
+ SHL2ADD_RRR_0_OPCODE_X1 = 34,
+ SHL2ADD_RRR_1_OPCODE_Y0 = 1,
+ SHL2ADD_RRR_1_OPCODE_Y1 = 1,
+ SHL3ADDX_RRR_0_OPCODE_X0 = 71,
+ SHL3ADDX_RRR_0_OPCODE_X1 = 35,
+ SHL3ADDX_RRR_7_OPCODE_Y0 = 3,
+ SHL3ADDX_RRR_7_OPCODE_Y1 = 3,
+ SHL3ADD_RRR_0_OPCODE_X0 = 72,
+ SHL3ADD_RRR_0_OPCODE_X1 = 36,
+ SHL3ADD_RRR_1_OPCODE_Y0 = 2,
+ SHL3ADD_RRR_1_OPCODE_Y1 = 2,
+ SHLI_SHIFT_OPCODE_X0 = 2,
+ SHLI_SHIFT_OPCODE_X1 = 2,
+ SHLI_SHIFT_OPCODE_Y0 = 1,
+ SHLI_SHIFT_OPCODE_Y1 = 1,
+ SHLXI_SHIFT_OPCODE_X0 = 3,
+ SHLXI_SHIFT_OPCODE_X1 = 3,
+ SHLX_RRR_0_OPCODE_X0 = 73,
+ SHLX_RRR_0_OPCODE_X1 = 37,
+ SHL_RRR_0_OPCODE_X0 = 74,
+ SHL_RRR_0_OPCODE_X1 = 38,
+ SHL_RRR_6_OPCODE_Y0 = 1,
+ SHL_RRR_6_OPCODE_Y1 = 1,
+ SHRSI_SHIFT_OPCODE_X0 = 4,
+ SHRSI_SHIFT_OPCODE_X1 = 4,
+ SHRSI_SHIFT_OPCODE_Y0 = 2,
+ SHRSI_SHIFT_OPCODE_Y1 = 2,
+ SHRS_RRR_0_OPCODE_X0 = 75,
+ SHRS_RRR_0_OPCODE_X1 = 39,
+ SHRS_RRR_6_OPCODE_Y0 = 2,
+ SHRS_RRR_6_OPCODE_Y1 = 2,
+ SHRUI_SHIFT_OPCODE_X0 = 5,
+ SHRUI_SHIFT_OPCODE_X1 = 5,
+ SHRUI_SHIFT_OPCODE_Y0 = 3,
+ SHRUI_SHIFT_OPCODE_Y1 = 3,
+ SHRUXI_SHIFT_OPCODE_X0 = 6,
+ SHRUXI_SHIFT_OPCODE_X1 = 6,
+ SHRUX_RRR_0_OPCODE_X0 = 76,
+ SHRUX_RRR_0_OPCODE_X1 = 40,
+ SHRU_RRR_0_OPCODE_X0 = 77,
+ SHRU_RRR_0_OPCODE_X1 = 41,
+ SHRU_RRR_6_OPCODE_Y0 = 3,
+ SHRU_RRR_6_OPCODE_Y1 = 3,
+ SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78,
+ ST1_ADD_IMM8_OPCODE_X1 = 25,
+ ST1_OPCODE_Y2 = 0,
+ ST1_RRR_0_OPCODE_X1 = 42,
+ ST2_ADD_IMM8_OPCODE_X1 = 26,
+ ST2_OPCODE_Y2 = 1,
+ ST2_RRR_0_OPCODE_X1 = 43,
+ ST4_ADD_IMM8_OPCODE_X1 = 27,
+ ST4_OPCODE_Y2 = 2,
+ ST4_RRR_0_OPCODE_X1 = 44,
+ STNT1_ADD_IMM8_OPCODE_X1 = 28,
+ STNT1_RRR_0_OPCODE_X1 = 45,
+ STNT2_ADD_IMM8_OPCODE_X1 = 29,
+ STNT2_RRR_0_OPCODE_X1 = 46,
+ STNT4_ADD_IMM8_OPCODE_X1 = 30,
+ STNT4_RRR_0_OPCODE_X1 = 47,
+ STNT_ADD_IMM8_OPCODE_X1 = 31,
+ STNT_RRR_0_OPCODE_X1 = 48,
+ ST_ADD_IMM8_OPCODE_X1 = 32,
+ ST_OPCODE_Y2 = 3,
+ ST_RRR_0_OPCODE_X1 = 49,
+ SUBXSC_RRR_0_OPCODE_X0 = 79,
+ SUBXSC_RRR_0_OPCODE_X1 = 50,
+ SUBX_RRR_0_OPCODE_X0 = 80,
+ SUBX_RRR_0_OPCODE_X1 = 51,
+ SUBX_RRR_0_OPCODE_Y0 = 2,
+ SUBX_RRR_0_OPCODE_Y1 = 2,
+ SUB_RRR_0_OPCODE_X0 = 81,
+ SUB_RRR_0_OPCODE_X1 = 52,
+ SUB_RRR_0_OPCODE_Y0 = 3,
+ SUB_RRR_0_OPCODE_Y1 = 3,
+ SWINT0_UNARY_OPCODE_X1 = 34,
+ SWINT1_UNARY_OPCODE_X1 = 35,
+ SWINT2_UNARY_OPCODE_X1 = 36,
+ SWINT3_UNARY_OPCODE_X1 = 37,
+ TBLIDXB0_UNARY_OPCODE_X0 = 9,
+ TBLIDXB0_UNARY_OPCODE_Y0 = 9,
+ TBLIDXB1_UNARY_OPCODE_X0 = 10,
+ TBLIDXB1_UNARY_OPCODE_Y0 = 10,
+ TBLIDXB2_UNARY_OPCODE_X0 = 11,
+ TBLIDXB2_UNARY_OPCODE_Y0 = 11,
+ TBLIDXB3_UNARY_OPCODE_X0 = 12,
+ TBLIDXB3_UNARY_OPCODE_Y0 = 12,
+ UNARY_RRR_0_OPCODE_X0 = 82,
+ UNARY_RRR_0_OPCODE_X1 = 53,
+ UNARY_RRR_1_OPCODE_Y0 = 3,
+ UNARY_RRR_1_OPCODE_Y1 = 3,
+ V1ADDI_IMM8_OPCODE_X0 = 8,
+ V1ADDI_IMM8_OPCODE_X1 = 33,
+ V1ADDUC_RRR_0_OPCODE_X0 = 83,
+ V1ADDUC_RRR_0_OPCODE_X1 = 54,
+ V1ADD_RRR_0_OPCODE_X0 = 84,
+ V1ADD_RRR_0_OPCODE_X1 = 55,
+ V1ADIFFU_RRR_0_OPCODE_X0 = 85,
+ V1AVGU_RRR_0_OPCODE_X0 = 86,
+ V1CMPEQI_IMM8_OPCODE_X0 = 9,
+ V1CMPEQI_IMM8_OPCODE_X1 = 34,
+ V1CMPEQ_RRR_0_OPCODE_X0 = 87,
+ V1CMPEQ_RRR_0_OPCODE_X1 = 56,
+ V1CMPLES_RRR_0_OPCODE_X0 = 88,
+ V1CMPLES_RRR_0_OPCODE_X1 = 57,
+ V1CMPLEU_RRR_0_OPCODE_X0 = 89,
+ V1CMPLEU_RRR_0_OPCODE_X1 = 58,
+ V1CMPLTSI_IMM8_OPCODE_X0 = 10,
+ V1CMPLTSI_IMM8_OPCODE_X1 = 35,
+ V1CMPLTS_RRR_0_OPCODE_X0 = 90,
+ V1CMPLTS_RRR_0_OPCODE_X1 = 59,
+ V1CMPLTUI_IMM8_OPCODE_X0 = 11,
+ V1CMPLTUI_IMM8_OPCODE_X1 = 36,
+ V1CMPLTU_RRR_0_OPCODE_X0 = 91,
+ V1CMPLTU_RRR_0_OPCODE_X1 = 60,
+ V1CMPNE_RRR_0_OPCODE_X0 = 92,
+ V1CMPNE_RRR_0_OPCODE_X1 = 61,
+ V1DDOTPUA_RRR_0_OPCODE_X0 = 161,
+ V1DDOTPUSA_RRR_0_OPCODE_X0 = 93,
+ V1DDOTPUS_RRR_0_OPCODE_X0 = 94,
+ V1DDOTPU_RRR_0_OPCODE_X0 = 162,
+ V1DOTPA_RRR_0_OPCODE_X0 = 95,
+ V1DOTPUA_RRR_0_OPCODE_X0 = 163,
+ V1DOTPUSA_RRR_0_OPCODE_X0 = 96,
+ V1DOTPUS_RRR_0_OPCODE_X0 = 97,
+ V1DOTPU_RRR_0_OPCODE_X0 = 164,
+ V1DOTP_RRR_0_OPCODE_X0 = 98,
+ V1INT_H_RRR_0_OPCODE_X0 = 99,
+ V1INT_H_RRR_0_OPCODE_X1 = 62,
+ V1INT_L_RRR_0_OPCODE_X0 = 100,
+ V1INT_L_RRR_0_OPCODE_X1 = 63,
+ V1MAXUI_IMM8_OPCODE_X0 = 12,
+ V1MAXUI_IMM8_OPCODE_X1 = 37,
+ V1MAXU_RRR_0_OPCODE_X0 = 101,
+ V1MAXU_RRR_0_OPCODE_X1 = 64,
+ V1MINUI_IMM8_OPCODE_X0 = 13,
+ V1MINUI_IMM8_OPCODE_X1 = 38,
+ V1MINU_RRR_0_OPCODE_X0 = 102,
+ V1MINU_RRR_0_OPCODE_X1 = 65,
+ V1MNZ_RRR_0_OPCODE_X0 = 103,
+ V1MNZ_RRR_0_OPCODE_X1 = 66,
+ V1MULTU_RRR_0_OPCODE_X0 = 104,
+ V1MULUS_RRR_0_OPCODE_X0 = 105,
+ V1MULU_RRR_0_OPCODE_X0 = 106,
+ V1MZ_RRR_0_OPCODE_X0 = 107,
+ V1MZ_RRR_0_OPCODE_X1 = 67,
+ V1SADAU_RRR_0_OPCODE_X0 = 108,
+ V1SADU_RRR_0_OPCODE_X0 = 109,
+ V1SHLI_SHIFT_OPCODE_X0 = 7,
+ V1SHLI_SHIFT_OPCODE_X1 = 7,
+ V1SHL_RRR_0_OPCODE_X0 = 110,
+ V1SHL_RRR_0_OPCODE_X1 = 68,
+ V1SHRSI_SHIFT_OPCODE_X0 = 8,
+ V1SHRSI_SHIFT_OPCODE_X1 = 8,
+ V1SHRS_RRR_0_OPCODE_X0 = 111,
+ V1SHRS_RRR_0_OPCODE_X1 = 69,
+ V1SHRUI_SHIFT_OPCODE_X0 = 9,
+ V1SHRUI_SHIFT_OPCODE_X1 = 9,
+ V1SHRU_RRR_0_OPCODE_X0 = 112,
+ V1SHRU_RRR_0_OPCODE_X1 = 70,
+ V1SUBUC_RRR_0_OPCODE_X0 = 113,
+ V1SUBUC_RRR_0_OPCODE_X1 = 71,
+ V1SUB_RRR_0_OPCODE_X0 = 114,
+ V1SUB_RRR_0_OPCODE_X1 = 72,
+ V2ADDI_IMM8_OPCODE_X0 = 14,
+ V2ADDI_IMM8_OPCODE_X1 = 39,
+ V2ADDSC_RRR_0_OPCODE_X0 = 115,
+ V2ADDSC_RRR_0_OPCODE_X1 = 73,
+ V2ADD_RRR_0_OPCODE_X0 = 116,
+ V2ADD_RRR_0_OPCODE_X1 = 74,
+ V2ADIFFS_RRR_0_OPCODE_X0 = 117,
+ V2AVGS_RRR_0_OPCODE_X0 = 118,
+ V2CMPEQI_IMM8_OPCODE_X0 = 15,
+ V2CMPEQI_IMM8_OPCODE_X1 = 40,
+ V2CMPEQ_RRR_0_OPCODE_X0 = 119,
+ V2CMPEQ_RRR_0_OPCODE_X1 = 75,
+ V2CMPLES_RRR_0_OPCODE_X0 = 120,
+ V2CMPLES_RRR_0_OPCODE_X1 = 76,
+ V2CMPLEU_RRR_0_OPCODE_X0 = 121,
+ V2CMPLEU_RRR_0_OPCODE_X1 = 77,
+ V2CMPLTSI_IMM8_OPCODE_X0 = 16,
+ V2CMPLTSI_IMM8_OPCODE_X1 = 41,
+ V2CMPLTS_RRR_0_OPCODE_X0 = 122,
+ V2CMPLTS_RRR_0_OPCODE_X1 = 78,
+ V2CMPLTUI_IMM8_OPCODE_X0 = 17,
+ V2CMPLTUI_IMM8_OPCODE_X1 = 42,
+ V2CMPLTU_RRR_0_OPCODE_X0 = 123,
+ V2CMPLTU_RRR_0_OPCODE_X1 = 79,
+ V2CMPNE_RRR_0_OPCODE_X0 = 124,
+ V2CMPNE_RRR_0_OPCODE_X1 = 80,
+ V2DOTPA_RRR_0_OPCODE_X0 = 125,
+ V2DOTP_RRR_0_OPCODE_X0 = 126,
+ V2INT_H_RRR_0_OPCODE_X0 = 127,
+ V2INT_H_RRR_0_OPCODE_X1 = 81,
+ V2INT_L_RRR_0_OPCODE_X0 = 128,
+ V2INT_L_RRR_0_OPCODE_X1 = 82,
+ V2MAXSI_IMM8_OPCODE_X0 = 18,
+ V2MAXSI_IMM8_OPCODE_X1 = 43,
+ V2MAXS_RRR_0_OPCODE_X0 = 129,
+ V2MAXS_RRR_0_OPCODE_X1 = 83,
+ V2MINSI_IMM8_OPCODE_X0 = 19,
+ V2MINSI_IMM8_OPCODE_X1 = 44,
+ V2MINS_RRR_0_OPCODE_X0 = 130,
+ V2MINS_RRR_0_OPCODE_X1 = 84,
+ V2MNZ_RRR_0_OPCODE_X0 = 131,
+ V2MNZ_RRR_0_OPCODE_X1 = 85,
+ V2MULFSC_RRR_0_OPCODE_X0 = 132,
+ V2MULS_RRR_0_OPCODE_X0 = 133,
+ V2MULTS_RRR_0_OPCODE_X0 = 134,
+ V2MZ_RRR_0_OPCODE_X0 = 135,
+ V2MZ_RRR_0_OPCODE_X1 = 86,
+ V2PACKH_RRR_0_OPCODE_X0 = 136,
+ V2PACKH_RRR_0_OPCODE_X1 = 87,
+ V2PACKL_RRR_0_OPCODE_X0 = 137,
+ V2PACKL_RRR_0_OPCODE_X1 = 88,
+ V2PACKUC_RRR_0_OPCODE_X0 = 138,
+ V2PACKUC_RRR_0_OPCODE_X1 = 89,
+ V2SADAS_RRR_0_OPCODE_X0 = 139,
+ V2SADAU_RRR_0_OPCODE_X0 = 140,
+ V2SADS_RRR_0_OPCODE_X0 = 141,
+ V2SADU_RRR_0_OPCODE_X0 = 142,
+ V2SHLI_SHIFT_OPCODE_X0 = 10,
+ V2SHLI_SHIFT_OPCODE_X1 = 10,
+ V2SHLSC_RRR_0_OPCODE_X0 = 143,
+ V2SHLSC_RRR_0_OPCODE_X1 = 90,
+ V2SHL_RRR_0_OPCODE_X0 = 144,
+ V2SHL_RRR_0_OPCODE_X1 = 91,
+ V2SHRSI_SHIFT_OPCODE_X0 = 11,
+ V2SHRSI_SHIFT_OPCODE_X1 = 11,
+ V2SHRS_RRR_0_OPCODE_X0 = 145,
+ V2SHRS_RRR_0_OPCODE_X1 = 92,
+ V2SHRUI_SHIFT_OPCODE_X0 = 12,
+ V2SHRUI_SHIFT_OPCODE_X1 = 12,
+ V2SHRU_RRR_0_OPCODE_X0 = 146,
+ V2SHRU_RRR_0_OPCODE_X1 = 93,
+ V2SUBSC_RRR_0_OPCODE_X0 = 147,
+ V2SUBSC_RRR_0_OPCODE_X1 = 94,
+ V2SUB_RRR_0_OPCODE_X0 = 148,
+ V2SUB_RRR_0_OPCODE_X1 = 95,
+ V4ADDSC_RRR_0_OPCODE_X0 = 149,
+ V4ADDSC_RRR_0_OPCODE_X1 = 96,
+ V4ADD_RRR_0_OPCODE_X0 = 150,
+ V4ADD_RRR_0_OPCODE_X1 = 97,
+ V4INT_H_RRR_0_OPCODE_X0 = 151,
+ V4INT_H_RRR_0_OPCODE_X1 = 98,
+ V4INT_L_RRR_0_OPCODE_X0 = 152,
+ V4INT_L_RRR_0_OPCODE_X1 = 99,
+ V4PACKSC_RRR_0_OPCODE_X0 = 153,
+ V4PACKSC_RRR_0_OPCODE_X1 = 100,
+ V4SHLSC_RRR_0_OPCODE_X0 = 154,
+ V4SHLSC_RRR_0_OPCODE_X1 = 101,
+ V4SHL_RRR_0_OPCODE_X0 = 155,
+ V4SHL_RRR_0_OPCODE_X1 = 102,
+ V4SHRS_RRR_0_OPCODE_X0 = 156,
+ V4SHRS_RRR_0_OPCODE_X1 = 103,
+ V4SHRU_RRR_0_OPCODE_X0 = 157,
+ V4SHRU_RRR_0_OPCODE_X1 = 104,
+ V4SUBSC_RRR_0_OPCODE_X0 = 158,
+ V4SUBSC_RRR_0_OPCODE_X1 = 105,
+ V4SUB_RRR_0_OPCODE_X0 = 159,
+ V4SUB_RRR_0_OPCODE_X1 = 106,
+ WH64_UNARY_OPCODE_X1 = 38,
+ XORI_IMM8_OPCODE_X0 = 20,
+ XORI_IMM8_OPCODE_X1 = 45,
+ XOR_RRR_0_OPCODE_X0 = 160,
+ XOR_RRR_0_OPCODE_X1 = 107,
+ XOR_RRR_5_OPCODE_Y0 = 3,
+ XOR_RRR_5_OPCODE_Y1 = 3
+};
+
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* __ARCH_OPCODE_H__ */
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 05/33] target-tilegx: Modify opcode_tilegx.h to fit QEMU usage
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (3 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 04/33] target-tilegx: Add opcode basic implementation from Tilera Corporation Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 06/33] target-tilegx: Modify _SPECIAL_ opcodes Richard Henderson
` (27 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, Chen Gang, xili_gchen_5257, peter.maydell
From: Chen Gang <xili_gchen_5257@hotmail.com>
Use 'inline' instead of '__inline', and also use 'uint64_t' instead of
"unsigned long long"
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <BLU436-SMTP1945B04384351D5EE7D9DECB9660@phx.gbl>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/opcode_tilegx.h | 220 +++++++++++++++++++++---------------------
1 file changed, 110 insertions(+), 110 deletions(-)
diff --git a/target-tilegx/opcode_tilegx.h b/target-tilegx/opcode_tilegx.h
index d76ff2d..33b71a9 100644
--- a/target-tilegx/opcode_tilegx.h
+++ b/target-tilegx/opcode_tilegx.h
@@ -23,7 +23,7 @@
#ifndef __ASSEMBLER__
-typedef unsigned long long tilegx_bundle_bits;
+typedef uint64_t tilegx_bundle_bits;
/* These are the bits that determine if a bundle is in the X encoding. */
#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
@@ -66,360 +66,360 @@ typedef tilegx_bundle_bits tile_bundle_bits;
/* 64-bit pattern for a { bpt ; nop } bundle. */
#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
-static __inline unsigned int
+static inline unsigned int
get_BFEnd_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 24)) & 0xf);
}
-static __inline unsigned int
+static inline unsigned int
get_BFStart_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 18)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_BrOff_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 31)) & 0x0000003f) |
(((unsigned int)(n >> 37)) & 0x0001ffc0);
}
-static __inline unsigned int
+static inline unsigned int
get_BrType_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 54)) & 0x1f);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_Imm8_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 31)) & 0x0000003f) |
(((unsigned int)(n >> 43)) & 0x000000c0);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 0)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 31)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 0)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 31)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm16_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0xffff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm16_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0xffff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 20)) & 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 51)) & 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_JumpOff_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 31)) & 0x7ffffff);
}
-static __inline unsigned int
+static inline unsigned int
get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 58)) & 0x1);
}
-static __inline unsigned int
+static inline unsigned int
get_MF_Imm14_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 37)) & 0x3fff);
}
-static __inline unsigned int
+static inline unsigned int
get_MT_Imm14_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 31)) & 0x0000003f) |
(((unsigned int)(n >> 37)) & 0x00003fc0);
}
-static __inline unsigned int
+static inline unsigned int
get_Mode(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 62)) & 0x3);
}
-static __inline unsigned int
+static inline unsigned int
get_Opcode_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 28)) & 0x7);
}
-static __inline unsigned int
+static inline unsigned int
get_Opcode_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 59)) & 0x7);
}
-static __inline unsigned int
+static inline unsigned int
get_Opcode_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 27)) & 0xf);
}
-static __inline unsigned int
+static inline unsigned int
get_Opcode_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 58)) & 0xf);
}
-static __inline unsigned int
+static inline unsigned int
get_Opcode_Y2(tilegx_bundle_bits n)
{
return (((n >> 26)) & 0x00000001) |
(((unsigned int)(n >> 56)) & 0x00000002);
}
-static __inline unsigned int
+static inline unsigned int
get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 18)) & 0x3ff);
}
-static __inline unsigned int
+static inline unsigned int
get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 49)) & 0x3ff);
}
-static __inline unsigned int
+static inline unsigned int
get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 18)) & 0x3);
}
-static __inline unsigned int
+static inline unsigned int
get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 49)) & 0x3);
}
-static __inline unsigned int
+static inline unsigned int
get_ShAmt_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_ShAmt_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_ShAmt_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_ShAmt_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 18)) & 0x3ff);
}
-static __inline unsigned int
+static inline unsigned int
get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 49)) & 0x3ff);
}
-static __inline unsigned int
+static inline unsigned int
get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 18)) & 0x3);
}
-static __inline unsigned int
+static inline unsigned int
get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 49)) & 0x3);
}
-static __inline unsigned int
+static inline unsigned int
get_SrcA_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 6)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_SrcA_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 37)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_SrcA_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 6)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_SrcA_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 37)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_SrcA_Y2(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 20)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_SrcBDest_Y2(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 51)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_SrcB_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_SrcB_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_SrcB_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_SrcB_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0x3f);
}
-static __inline int
+static inline int
sign_extend(int n, int num_bits)
{
int shift = (int)(sizeof(int) * 8 - num_bits);
@@ -428,28 +428,28 @@ sign_extend(int n, int num_bits)
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_BFEnd_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 12);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_BFOpcodeExtension_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0xf) << 24);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_BFStart_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 18);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_BrOff_X1(int num)
{
const unsigned int n = (unsigned int)num;
@@ -457,14 +457,14 @@ create_BrOff_X1(int num)
(((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_BrType_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Dest_Imm8_X1(int num)
{
const unsigned int n = (unsigned int)num;
@@ -472,112 +472,112 @@ create_Dest_Imm8_X1(int num)
(((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Dest_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 0);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Dest_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Dest_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 0);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Dest_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Imm16_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0xffff) << 12);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Imm16_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Imm8OpcodeExtension_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0xff) << 20);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Imm8OpcodeExtension_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0xff)) << 51);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Imm8_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0xff) << 12);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Imm8_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0xff)) << 43);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Imm8_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0xff) << 12);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Imm8_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0xff)) << 43);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_JumpOff_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_JumpOpcodeExtension_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x1)) << 58);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_MF_Imm14_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_MT_Imm14_X1(int num)
{
const unsigned int n = (unsigned int)num;
@@ -585,42 +585,42 @@ create_MT_Imm14_X1(int num)
(((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Mode(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3)) << 62);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Opcode_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x7) << 28);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Opcode_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x7)) << 59);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Opcode_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0xf) << 27);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Opcode_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0xf)) << 58);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_Opcode_Y2(int num)
{
const unsigned int n = (unsigned int)num;
@@ -628,182 +628,182 @@ create_Opcode_Y2(int num)
(((tilegx_bundle_bits)(n & 0x00000002)) << 56);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_RRROpcodeExtension_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3ff) << 18);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_RRROpcodeExtension_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_RRROpcodeExtension_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3) << 18);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_RRROpcodeExtension_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3)) << 49);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_ShAmt_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 12);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_ShAmt_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_ShAmt_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 12);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_ShAmt_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_ShiftOpcodeExtension_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3ff) << 18);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_ShiftOpcodeExtension_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_ShiftOpcodeExtension_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3) << 18);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_ShiftOpcodeExtension_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3)) << 49);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_SrcA_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 6);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_SrcA_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_SrcA_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 6);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_SrcA_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_SrcA_Y2(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 20);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_SrcBDest_Y2(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_SrcB_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 12);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_SrcB_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_SrcB_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 12);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_SrcB_Y1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_UnaryOpcodeExtension_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 12);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_UnaryOpcodeExtension_X1(int num)
{
const unsigned int n = (unsigned int)num;
return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_UnaryOpcodeExtension_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 12);
}
-static __inline tilegx_bundle_bits
+static inline tilegx_bundle_bits
create_UnaryOpcodeExtension_Y1(int num)
{
const unsigned int n = (unsigned int)num;
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 06/33] target-tilegx: Modify _SPECIAL_ opcodes
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (4 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 05/33] target-tilegx: Modify opcode_tilegx.h to fit QEMU usage Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-29 14:29 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 07/33] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 Richard Henderson
` (26 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Both ADDX_SPECIAL_0_OPCODE_Y1 and ADD_SPECIAL_0_OPCODE_Y1
do not appear to be "special" in any way, except that they
don't follow the normal naming convention using _RRR_.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/opcode_tilegx.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-tilegx/opcode_tilegx.h b/target-tilegx/opcode_tilegx.h
index 33b71a9..3b8bf4f 100644
--- a/target-tilegx/opcode_tilegx.h
+++ b/target-tilegx/opcode_tilegx.h
@@ -830,11 +830,11 @@ enum
ADDX_RRR_0_OPCODE_X0 = 2,
ADDX_RRR_0_OPCODE_X1 = 2,
ADDX_RRR_0_OPCODE_Y0 = 0,
- ADDX_SPECIAL_0_OPCODE_Y1 = 0,
+ ADDX_RRR_0_OPCODE_Y1 = 0,
ADD_RRR_0_OPCODE_X0 = 3,
ADD_RRR_0_OPCODE_X1 = 3,
ADD_RRR_0_OPCODE_Y0 = 1,
- ADD_SPECIAL_0_OPCODE_Y1 = 1,
+ ADD_RRR_0_OPCODE_Y1 = 1,
ANDI_IMM8_OPCODE_X0 = 3,
ANDI_IMM8_OPCODE_X1 = 3,
ANDI_OPCODE_Y0 = 2,
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 07/33] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (5 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 06/33] target-tilegx: Modify _SPECIAL_ opcodes Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-24 16:29 ` Peter Maydell
` (2 more replies)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 08/33] target-tilegx: Add special register information from Tilera Corporation Richard Henderson
` (25 subsequent siblings)
32 siblings, 3 replies; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
An obvious typo in the mnemonic here.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/opcode_tilegx.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-tilegx/opcode_tilegx.h b/target-tilegx/opcode_tilegx.h
index 3b8bf4f..989436d 100644
--- a/target-tilegx/opcode_tilegx.h
+++ b/target-tilegx/opcode_tilegx.h
@@ -1015,7 +1015,7 @@ enum
LD_UNARY_OPCODE_X1 = 29,
LNK_UNARY_OPCODE_X1 = 30,
LNK_UNARY_OPCODE_Y1 = 14,
- LWNA_ADD_IMM8_OPCODE_X1 = 21,
+ LDNA_ADD_IMM8_OPCODE_X1 = 21,
MFSPR_IMM8_OPCODE_X1 = 22,
MF_UNARY_OPCODE_X1 = 31,
MM_BF_OPCODE_X0 = 7,
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 08/33] target-tilegx: Add special register information from Tilera Corporation
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (6 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 07/33] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 09/33] target-tilegx: Add cpu basic features for linux-user Richard Henderson
` (24 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, Chen Gang, xili_gchen_5257, peter.maydell
From: Chen Gang <xili_gchen_5257@hotmail.com>
The related copy is from Linux kernel "arch/tile/include/uapi/arch/
spr_def_64.h".
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <BLU436-SMTP1093D605AAE9B4837B564B8B9660@phx.gbl>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/spr_def_64.h | 216 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 216 insertions(+)
create mode 100644 target-tilegx/spr_def_64.h
diff --git a/target-tilegx/spr_def_64.h b/target-tilegx/spr_def_64.h
new file mode 100644
index 0000000..67a6c17
--- /dev/null
+++ b/target-tilegx/spr_def_64.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __DOXYGEN__
+
+#ifndef __ARCH_SPR_DEF_64_H__
+#define __ARCH_SPR_DEF_64_H__
+
+#define SPR_AUX_PERF_COUNT_0 0x2105
+#define SPR_AUX_PERF_COUNT_1 0x2106
+#define SPR_AUX_PERF_COUNT_CTL 0x2107
+#define SPR_AUX_PERF_COUNT_STS 0x2108
+#define SPR_CMPEXCH_VALUE 0x2780
+#define SPR_CYCLE 0x2781
+#define SPR_DONE 0x2705
+#define SPR_DSTREAM_PF 0x2706
+#define SPR_EVENT_BEGIN 0x2782
+#define SPR_EVENT_END 0x2783
+#define SPR_EX_CONTEXT_0_0 0x2580
+#define SPR_EX_CONTEXT_0_1 0x2581
+#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0
+#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3
+#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3
+#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2
+#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1
+#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4
+#define SPR_EX_CONTEXT_1_0 0x2480
+#define SPR_EX_CONTEXT_1_1 0x2481
+#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0
+#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3
+#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3
+#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
+#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
+#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4
+#define SPR_EX_CONTEXT_2_0 0x2380
+#define SPR_EX_CONTEXT_2_1 0x2381
+#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
+#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
+#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3
+#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
+#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
+#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4
+#define SPR_FAIL 0x2707
+#define SPR_IDN_AVAIL_EN 0x1a05
+#define SPR_IDN_DATA_AVAIL 0x0a80
+#define SPR_IDN_DEADLOCK_TIMEOUT 0x1806
+#define SPR_IDN_DEMUX_COUNT_0 0x0a05
+#define SPR_IDN_DEMUX_COUNT_1 0x0a06
+#define SPR_IDN_DIRECTION_PROTECT 0x1405
+#define SPR_IDN_PENDING 0x0a08
+#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1
+#define SPR_INTCTRL_0_STATUS 0x2505
+#define SPR_INTCTRL_1_STATUS 0x2405
+#define SPR_INTCTRL_2_STATUS 0x2305
+#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708
+#define SPR_INTERRUPT_MASK_0 0x2506
+#define SPR_INTERRUPT_MASK_1 0x2406
+#define SPR_INTERRUPT_MASK_2 0x2306
+#define SPR_INTERRUPT_MASK_RESET_0 0x2507
+#define SPR_INTERRUPT_MASK_RESET_1 0x2407
+#define SPR_INTERRUPT_MASK_RESET_2 0x2307
+#define SPR_INTERRUPT_MASK_SET_0 0x2508
+#define SPR_INTERRUPT_MASK_SET_1 0x2408
+#define SPR_INTERRUPT_MASK_SET_2 0x2308
+#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509
+#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409
+#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309
+#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209
+#define SPR_IPI_EVENT_0 0x1f05
+#define SPR_IPI_EVENT_1 0x1e05
+#define SPR_IPI_EVENT_2 0x1d05
+#define SPR_IPI_EVENT_RESET_0 0x1f06
+#define SPR_IPI_EVENT_RESET_1 0x1e06
+#define SPR_IPI_EVENT_RESET_2 0x1d06
+#define SPR_IPI_EVENT_SET_0 0x1f07
+#define SPR_IPI_EVENT_SET_1 0x1e07
+#define SPR_IPI_EVENT_SET_2 0x1d07
+#define SPR_IPI_MASK_0 0x1f08
+#define SPR_IPI_MASK_1 0x1e08
+#define SPR_IPI_MASK_2 0x1d08
+#define SPR_IPI_MASK_RESET_0 0x1f09
+#define SPR_IPI_MASK_RESET_1 0x1e09
+#define SPR_IPI_MASK_RESET_2 0x1d09
+#define SPR_IPI_MASK_SET_0 0x1f0a
+#define SPR_IPI_MASK_SET_1 0x1e0a
+#define SPR_IPI_MASK_SET_2 0x1d0a
+#define SPR_MPL_AUX_PERF_COUNT_SET_0 0x2100
+#define SPR_MPL_AUX_PERF_COUNT_SET_1 0x2101
+#define SPR_MPL_AUX_PERF_COUNT_SET_2 0x2102
+#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700
+#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701
+#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702
+#define SPR_MPL_IDN_ACCESS_SET_0 0x0a00
+#define SPR_MPL_IDN_ACCESS_SET_1 0x0a01
+#define SPR_MPL_IDN_ACCESS_SET_2 0x0a02
+#define SPR_MPL_IDN_AVAIL_SET_0 0x1a00
+#define SPR_MPL_IDN_AVAIL_SET_1 0x1a01
+#define SPR_MPL_IDN_AVAIL_SET_2 0x1a02
+#define SPR_MPL_IDN_COMPLETE_SET_0 0x0500
+#define SPR_MPL_IDN_COMPLETE_SET_1 0x0501
+#define SPR_MPL_IDN_COMPLETE_SET_2 0x0502
+#define SPR_MPL_IDN_FIREWALL_SET_0 0x1400
+#define SPR_MPL_IDN_FIREWALL_SET_1 0x1401
+#define SPR_MPL_IDN_FIREWALL_SET_2 0x1402
+#define SPR_MPL_IDN_TIMER_SET_0 0x1800
+#define SPR_MPL_IDN_TIMER_SET_1 0x1801
+#define SPR_MPL_IDN_TIMER_SET_2 0x1802
+#define SPR_MPL_INTCTRL_0_SET_0 0x2500
+#define SPR_MPL_INTCTRL_0_SET_1 0x2501
+#define SPR_MPL_INTCTRL_0_SET_2 0x2502
+#define SPR_MPL_INTCTRL_1_SET_0 0x2400
+#define SPR_MPL_INTCTRL_1_SET_1 0x2401
+#define SPR_MPL_INTCTRL_1_SET_2 0x2402
+#define SPR_MPL_INTCTRL_2_SET_0 0x2300
+#define SPR_MPL_INTCTRL_2_SET_1 0x2301
+#define SPR_MPL_INTCTRL_2_SET_2 0x2302
+#define SPR_MPL_IPI_0 0x1f04
+#define SPR_MPL_IPI_0_SET_0 0x1f00
+#define SPR_MPL_IPI_0_SET_1 0x1f01
+#define SPR_MPL_IPI_0_SET_2 0x1f02
+#define SPR_MPL_IPI_1 0x1e04
+#define SPR_MPL_IPI_1_SET_0 0x1e00
+#define SPR_MPL_IPI_1_SET_1 0x1e01
+#define SPR_MPL_IPI_1_SET_2 0x1e02
+#define SPR_MPL_IPI_2 0x1d04
+#define SPR_MPL_IPI_2_SET_0 0x1d00
+#define SPR_MPL_IPI_2_SET_1 0x1d01
+#define SPR_MPL_IPI_2_SET_2 0x1d02
+#define SPR_MPL_PERF_COUNT_SET_0 0x2000
+#define SPR_MPL_PERF_COUNT_SET_1 0x2001
+#define SPR_MPL_PERF_COUNT_SET_2 0x2002
+#define SPR_MPL_UDN_ACCESS_SET_0 0x0b00
+#define SPR_MPL_UDN_ACCESS_SET_1 0x0b01
+#define SPR_MPL_UDN_ACCESS_SET_2 0x0b02
+#define SPR_MPL_UDN_AVAIL_SET_0 0x1b00
+#define SPR_MPL_UDN_AVAIL_SET_1 0x1b01
+#define SPR_MPL_UDN_AVAIL_SET_2 0x1b02
+#define SPR_MPL_UDN_COMPLETE_SET_0 0x0600
+#define SPR_MPL_UDN_COMPLETE_SET_1 0x0601
+#define SPR_MPL_UDN_COMPLETE_SET_2 0x0602
+#define SPR_MPL_UDN_FIREWALL_SET_0 0x1500
+#define SPR_MPL_UDN_FIREWALL_SET_1 0x1501
+#define SPR_MPL_UDN_FIREWALL_SET_2 0x1502
+#define SPR_MPL_UDN_TIMER_SET_0 0x1900
+#define SPR_MPL_UDN_TIMER_SET_1 0x1901
+#define SPR_MPL_UDN_TIMER_SET_2 0x1902
+#define SPR_MPL_WORLD_ACCESS_SET_0 0x2700
+#define SPR_MPL_WORLD_ACCESS_SET_1 0x2701
+#define SPR_MPL_WORLD_ACCESS_SET_2 0x2702
+#define SPR_PASS 0x2709
+#define SPR_PERF_COUNT_0 0x2005
+#define SPR_PERF_COUNT_1 0x2006
+#define SPR_PERF_COUNT_CTL 0x2007
+#define SPR_PERF_COUNT_DN_CTL 0x2008
+#define SPR_PERF_COUNT_STS 0x2009
+#define SPR_PROC_STATUS 0x2784
+#define SPR_SIM_CONTROL 0x2785
+#define SPR_SINGLE_STEP_CONTROL_0 0x0405
+#define SPR_SINGLE_STEP_CONTROL_0__CANCELED_MASK 0x1
+#define SPR_SINGLE_STEP_CONTROL_0__INHIBIT_MASK 0x2
+#define SPR_SINGLE_STEP_CONTROL_1 0x0305
+#define SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK 0x1
+#define SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK 0x2
+#define SPR_SINGLE_STEP_CONTROL_2 0x0205
+#define SPR_SINGLE_STEP_CONTROL_2__CANCELED_MASK 0x1
+#define SPR_SINGLE_STEP_CONTROL_2__INHIBIT_MASK 0x2
+#define SPR_SINGLE_STEP_EN_0_0 0x250a
+#define SPR_SINGLE_STEP_EN_0_1 0x240a
+#define SPR_SINGLE_STEP_EN_0_2 0x230a
+#define SPR_SINGLE_STEP_EN_1_0 0x250b
+#define SPR_SINGLE_STEP_EN_1_1 0x240b
+#define SPR_SINGLE_STEP_EN_1_2 0x230b
+#define SPR_SINGLE_STEP_EN_2_0 0x250c
+#define SPR_SINGLE_STEP_EN_2_1 0x240c
+#define SPR_SINGLE_STEP_EN_2_2 0x230c
+#define SPR_SYSTEM_SAVE_0_0 0x2582
+#define SPR_SYSTEM_SAVE_0_1 0x2583
+#define SPR_SYSTEM_SAVE_0_2 0x2584
+#define SPR_SYSTEM_SAVE_0_3 0x2585
+#define SPR_SYSTEM_SAVE_1_0 0x2482
+#define SPR_SYSTEM_SAVE_1_1 0x2483
+#define SPR_SYSTEM_SAVE_1_2 0x2484
+#define SPR_SYSTEM_SAVE_1_3 0x2485
+#define SPR_SYSTEM_SAVE_2_0 0x2382
+#define SPR_SYSTEM_SAVE_2_1 0x2383
+#define SPR_SYSTEM_SAVE_2_2 0x2384
+#define SPR_SYSTEM_SAVE_2_3 0x2385
+#define SPR_TILE_COORD 0x270b
+#define SPR_TILE_RTF_HWM 0x270c
+#define SPR_TILE_TIMER_CONTROL 0x1605
+#define SPR_UDN_AVAIL_EN 0x1b05
+#define SPR_UDN_DATA_AVAIL 0x0b80
+#define SPR_UDN_DEADLOCK_TIMEOUT 0x1906
+#define SPR_UDN_DEMUX_COUNT_0 0x0b05
+#define SPR_UDN_DEMUX_COUNT_1 0x0b06
+#define SPR_UDN_DEMUX_COUNT_2 0x0b07
+#define SPR_UDN_DEMUX_COUNT_3 0x0b08
+#define SPR_UDN_DIRECTION_PROTECT 0x1505
+#define SPR_UDN_PENDING 0x0b0a
+#define SPR_WATCH_MASK 0x200a
+#define SPR_WATCH_VAL 0x200b
+
+#endif /* !defined(__ARCH_SPR_DEF_64_H__) */
+
+#endif /* !defined(__DOXYGEN__) */
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 09/33] target-tilegx: Add cpu basic features for linux-user
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (7 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 08/33] target-tilegx: Add special register information from Tilera Corporation Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 10/33] target-tilegx: Add several helpers for instructions translation Richard Henderson
` (23 subsequent siblings)
32 siblings, 0 replies; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, Chen Gang, xili_gchen_5257, peter.maydell
From: Chen Gang <xili_gchen_5257@hotmail.com>
It implements minimized cpu features for linux-user.
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <BLU436-SMTP114819BB03D853801AA9C3CB9660@phx.gbl>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/cpu.c | 170 ++++++++++++++++++++++++++++++++++++++++++++++++++
target-tilegx/cpu.h | 175 ++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 345 insertions(+)
create mode 100644 target-tilegx/cpu.c
create mode 100644 target-tilegx/cpu.h
diff --git a/target-tilegx/cpu.c b/target-tilegx/cpu.c
new file mode 100644
index 0000000..87aee24
--- /dev/null
+++ b/target-tilegx/cpu.c
@@ -0,0 +1,170 @@
+/*
+ * QEMU TILE-Gx CPU
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu.h"
+#include "qemu-common.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+
+static void tilegx_cpu_dump_state(CPUState *cs, FILE *f,
+ fprintf_function cpu_fprintf, int flags)
+{
+ static const char * const reg_names[TILEGX_R_COUNT] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+ "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
+ "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
+ "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr"
+ };
+
+ TileGXCPU *cpu = TILEGX_CPU(cs);
+ CPUTLGState *env = &cpu->env;
+ int i;
+
+ for (i = 0; i < TILEGX_R_COUNT; i++) {
+ cpu_fprintf(f, "%-4s" TARGET_FMT_lx "%s",
+ reg_names[i], env->regs[i],
+ (i % 4) == 3 ? "\n" : " ");
+ }
+ cpu_fprintf(f, "PC " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n",
+ env->pc, env->spregs[TILEGX_SPR_CMPEXCH]);
+}
+
+TileGXCPU *cpu_tilegx_init(const char *cpu_model)
+{
+ TileGXCPU *cpu;
+
+ cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU));
+
+ object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+
+ return cpu;
+}
+
+static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
+{
+ TileGXCPU *cpu = TILEGX_CPU(cs);
+
+ cpu->env.pc = value;
+}
+
+static bool tilegx_cpu_has_work(CPUState *cs)
+{
+ return true;
+}
+
+static void tilegx_cpu_reset(CPUState *s)
+{
+ TileGXCPU *cpu = TILEGX_CPU(s);
+ TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
+ CPUTLGState *env = &cpu->env;
+
+ tcc->parent_reset(s);
+
+ memset(env, 0, sizeof(CPUTLGState));
+ tlb_flush(s, 1);
+}
+
+static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+ CPUState *cs = CPU(dev);
+ TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
+
+ cpu_reset(cs);
+ qemu_init_vcpu(cs);
+
+ tcc->parent_realize(dev, errp);
+}
+
+static void tilegx_cpu_initfn(Object *obj)
+{
+ CPUState *cs = CPU(obj);
+ TileGXCPU *cpu = TILEGX_CPU(obj);
+ CPUTLGState *env = &cpu->env;
+ static bool tcg_initialized;
+
+ cs->env_ptr = env;
+ cpu_exec_init(cs, &error_abort);
+
+ if (tcg_enabled() && !tcg_initialized) {
+ tcg_initialized = true;
+ tilegx_tcg_init();
+ }
+}
+
+static void tilegx_cpu_do_interrupt(CPUState *cs)
+{
+ cs->exception_index = -1;
+}
+
+static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
+ int mmu_idx)
+{
+ cpu_dump_state(cs, stderr, fprintf, 0);
+ return 1;
+}
+
+static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+ if (interrupt_request & CPU_INTERRUPT_HARD) {
+ tilegx_cpu_do_interrupt(cs);
+ return true;
+ }
+ return false;
+}
+
+static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ CPUClass *cc = CPU_CLASS(oc);
+ TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
+
+ tcc->parent_realize = dc->realize;
+ dc->realize = tilegx_cpu_realizefn;
+
+ tcc->parent_reset = cc->reset;
+ cc->reset = tilegx_cpu_reset;
+
+ cc->has_work = tilegx_cpu_has_work;
+ cc->do_interrupt = tilegx_cpu_do_interrupt;
+ cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
+ cc->dump_state = tilegx_cpu_dump_state;
+ cc->set_pc = tilegx_cpu_set_pc;
+ cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
+ cc->gdb_num_core_regs = 0;
+}
+
+static const TypeInfo tilegx_cpu_type_info = {
+ .name = TYPE_TILEGX_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(TileGXCPU),
+ .instance_init = tilegx_cpu_initfn,
+ .class_size = sizeof(TileGXCPUClass),
+ .class_init = tilegx_cpu_class_init,
+};
+
+static void tilegx_cpu_register_types(void)
+{
+ type_register_static(&tilegx_cpu_type_info);
+}
+
+type_init(tilegx_cpu_register_types)
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
new file mode 100644
index 0000000..2c86cd3
--- /dev/null
+++ b/target-tilegx/cpu.h
@@ -0,0 +1,175 @@
+/*
+ * TILE-Gx virtual CPU header
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef CPU_TILEGX_H
+#define CPU_TILEGX_H
+
+#include "config.h"
+#include "qemu-common.h"
+
+#define TARGET_LONG_BITS 64
+
+#define CPUArchState struct CPUTLGState
+
+#include "exec/cpu-defs.h"
+
+
+/* TILE-Gx common register alias */
+#define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
+#define TILEGX_R_ERR 1 /* 1 register, for syscall errno flag */
+#define TILEGX_R_NR 10 /* 10 register, for syscall number */
+#define TILEGX_R_BP 52 /* 52 register, optional frame pointer */
+#define TILEGX_R_TP 53 /* TP register, thread local storage data */
+#define TILEGX_R_SP 54 /* SP register, stack pointer */
+#define TILEGX_R_LR 55 /* LR register, may save pc, but it is not pc */
+#define TILEGX_R_COUNT 56 /* Only 56 registers are really useful */
+#define TILEGX_R_SN 56 /* SN register, obsoleted, it likes zero register */
+#define TILEGX_R_IDN0 57 /* IDN0 register, cause IDN_ACCESS exception */
+#define TILEGX_R_IDN1 58 /* IDN1 register, cause IDN_ACCESS exception */
+#define TILEGX_R_UDN0 59 /* UDN0 register, cause UDN_ACCESS exception */
+#define TILEGX_R_UDN1 60 /* UDN1 register, cause UDN_ACCESS exception */
+#define TILEGX_R_UDN2 61 /* UDN2 register, cause UDN_ACCESS exception */
+#define TILEGX_R_UDN3 62 /* UDN3 register, cause UDN_ACCESS exception */
+#define TILEGX_R_ZERO 63 /* Zero register, always zero */
+#define TILEGX_R_NOREG 255 /* Invalid register value */
+
+/* TILE-Gx special registers used by outside */
+enum {
+ TILEGX_SPR_CMPEXCH = 0,
+ TILEGX_SPR_CRITICAL_SEC = 1,
+ TILEGX_SPR_SIM_CONTROL = 2,
+ TILEGX_SPR_COUNT
+};
+
+/* Exception numbers */
+typedef enum {
+ TILEGX_EXCP_NONE = 0,
+ TILEGX_EXCP_SYSCALL = 1,
+ TILEGX_EXCP_OPCODE_UNKNOWN = 0x101,
+ TILEGX_EXCP_OPCODE_UNIMPLEMENTED = 0x102,
+ TILEGX_EXCP_OPCODE_CMPEXCH = 0x103,
+ TILEGX_EXCP_OPCODE_CMPEXCH4 = 0x104,
+ TILEGX_EXCP_OPCODE_EXCH = 0x105,
+ TILEGX_EXCP_OPCODE_EXCH4 = 0x106,
+ TILEGX_EXCP_OPCODE_FETCHADD = 0x107,
+ TILEGX_EXCP_OPCODE_FETCHADD4 = 0x108,
+ TILEGX_EXCP_OPCODE_FETCHADDGEZ = 0x109,
+ TILEGX_EXCP_OPCODE_FETCHADDGEZ4 = 0x10a,
+ TILEGX_EXCP_OPCODE_FETCHAND = 0x10b,
+ TILEGX_EXCP_OPCODE_FETCHAND4 = 0x10c,
+ TILEGX_EXCP_OPCODE_FETCHOR = 0x10d,
+ TILEGX_EXCP_OPCODE_FETCHOR4 = 0x10e,
+ TILEGX_EXCP_REG_IDN_ACCESS = 0x181,
+ TILEGX_EXCP_REG_UDN_ACCESS = 0x182,
+ TILEGX_EXCP_UNALIGNMENT = 0x201,
+ TILEGX_EXCP_DBUG_BREAK = 0x301
+} TileExcp;
+
+typedef struct CPUTLGState {
+ uint64_t regs[TILEGX_R_COUNT]; /* Common used registers by outside */
+ uint64_t spregs[TILEGX_SPR_COUNT]; /* Special used registers by outside */
+ uint64_t pc; /* Current pc */
+
+#if defined(CONFIG_USER_ONLY)
+ uint32_t excparam; /* exception parameter */
+#endif
+
+ CPU_COMMON
+} CPUTLGState;
+
+#include "qom/cpu.h"
+
+#define TYPE_TILEGX_CPU "tilegx-cpu"
+
+#define TILEGX_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(TileGXCPUClass, (klass), TYPE_TILEGX_CPU)
+#define TILEGX_CPU(obj) \
+ OBJECT_CHECK(TileGXCPU, (obj), TYPE_TILEGX_CPU)
+#define TILEGX_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(TileGXCPUClass, (obj), TYPE_TILEGX_CPU)
+
+/**
+ * TileGXCPUClass:
+ * @parent_realize: The parent class' realize handler.
+ * @parent_reset: The parent class' reset handler.
+ *
+ * A Tile-Gx CPU model.
+ */
+typedef struct TileGXCPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ DeviceRealize parent_realize;
+ void (*parent_reset)(CPUState *cpu);
+} TileGXCPUClass;
+
+/**
+ * TileGXCPU:
+ * @env: #CPUTLGState
+ *
+ * A Tile-GX CPU.
+ */
+typedef struct TileGXCPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPUTLGState env;
+} TileGXCPU;
+
+static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
+{
+ return container_of(env, TileGXCPU, env);
+}
+
+#define ENV_GET_CPU(e) CPU(tilegx_env_get_cpu(e))
+
+#define ENV_OFFSET offsetof(TileGXCPU, env)
+
+/* TILE-Gx memory attributes */
+#define TARGET_PAGE_BITS 16 /* TILE-Gx uses 64KB page size */
+#define TARGET_PHYS_ADDR_SPACE_BITS 42
+#define TARGET_VIRT_ADDR_SPACE_BITS 64
+#define MMU_USER_IDX 0 /* Current memory operation is in user mode */
+
+#include "exec/cpu-all.h"
+
+void tilegx_tcg_init(void);
+int cpu_tilegx_exec(CPUState *s);
+int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc);
+
+TileGXCPU *cpu_tilegx_init(const char *cpu_model);
+
+#define cpu_init(cpu_model) CPU(cpu_tilegx_init(cpu_model))
+
+#define cpu_exec cpu_tilegx_exec
+#define cpu_gen_code cpu_tilegx_gen_code
+#define cpu_signal_handler cpu_tilegx_signal_handler
+
+static inline void cpu_get_tb_cpu_state(CPUTLGState *env, target_ulong *pc,
+ target_ulong *cs_base, int *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = 0;
+}
+
+#include "exec/exec-all.h"
+
+#endif
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 10/33] target-tilegx: Add several helpers for instructions translation
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (8 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 09/33] target-tilegx: Add cpu basic features for linux-user Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-29 14:37 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 11/33] target-tilegx: Framework for decoding bundles Richard Henderson
` (22 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, Chen Gang, xili_gchen_5257, peter.maydell
From: Chen Gang <xili_gchen_5257@hotmail.com>
The related instructions are exception, cntlz, cnttz, shufflebytes.
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
Message-Id: <BLU436-SMTP83F96FD8422BE49AFDC9DFB9660@phx.gbl>
[rth: Remove incorrect implementation of add_saturate.]
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/helper.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++
target-tilegx/helper.h | 4 +++
2 files changed, 74 insertions(+)
create mode 100644 target-tilegx/helper.c
create mode 100644 target-tilegx/helper.h
diff --git a/target-tilegx/helper.c b/target-tilegx/helper.c
new file mode 100644
index 0000000..ea66da0
--- /dev/null
+++ b/target-tilegx/helper.c
@@ -0,0 +1,70 @@
+/*
+ * QEMU TILE-Gx helpers
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu.h"
+#include "qemu-common.h"
+#include "exec/helper-proto.h"
+
+void helper_exception(CPUTLGState *env, uint32_t excp)
+{
+ CPUState *cs = CPU(tilegx_env_get_cpu(env));
+
+ cs->exception_index = excp;
+ cpu_loop_exit(cs);
+}
+
+uint64_t helper_cntlz(uint64_t arg)
+{
+ return clz64(arg);
+}
+
+uint64_t helper_cnttz(uint64_t arg)
+{
+ return ctz64(arg);
+}
+
+/*
+ * Functional Description
+ * uint64_t a = rf[SrcA];
+ * uint64_t b = rf[SrcB];
+ * uint64_t d = rf[Dest];
+ * uint64_t output = 0;
+ * unsigned int counter;
+ * for (counter = 0; counter < (WORD_SIZE / BYTE_SIZE); counter++)
+ * {
+ * int sel = getByte (b, counter) & 0xf;
+ * uint8_t byte = (sel < 8) ? getByte (d, sel) : getByte (a, (sel - 8));
+ * output = setByte (output, counter, byte);
+ * }
+ * rf[Dest] = output;
+ */
+uint64_t helper_shufflebytes(uint64_t dest, uint64_t srca, uint64_t srcb)
+{
+ uint64_t vdst = 0;
+ int count;
+
+ for (count = 0; count < 64; count += 8) {
+ uint64_t sel = srcb >> count;
+ uint64_t src = (sel & 8) ? srca : dest;
+ vdst |= ((src >> ((sel & 7) * 8)) & 0xff) << count;
+ }
+
+ return vdst;
+}
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
new file mode 100644
index 0000000..fd5517e
--- /dev/null
+++ b/target-tilegx/helper.h
@@ -0,0 +1,4 @@
+DEF_HELPER_2(exception, noreturn, env, i32)
+DEF_HELPER_FLAGS_1(cntlz, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 11/33] target-tilegx: Framework for decoding bundles
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (9 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 10/33] target-tilegx: Add several helpers for instructions translation Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-29 14:50 ` Peter Maydell
2015-08-29 21:08 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 12/33] target-tilegx: Generate SEGV properly Richard Henderson
` (21 subsequent siblings)
32 siblings, 2 replies; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 1145 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 1145 insertions(+)
create mode 100644 target-tilegx/translate.c
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
new file mode 100644
index 0000000..a2d597d
--- /dev/null
+++ b/target-tilegx/translate.c
@@ -0,0 +1,1145 @@
+/*
+ * QEMU TILE-Gx CPU
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu.h"
+#include "qemu/log.h"
+#include "disas/disas.h"
+#include "tcg-op.h"
+#include "exec/cpu_ldst.h"
+#include "opcode_tilegx.h"
+
+#define FMT64X "%016" PRIx64
+
+static TCGv_ptr cpu_env;
+static TCGv cpu_pc;
+static TCGv cpu_regs[TILEGX_R_COUNT];
+
+static const char * const reg_names[64] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+ "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
+ "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
+ "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr",
+ "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn2", "zero"
+};
+
+/* Modified registers are cached in temporaries until the end of the bundle. */
+typedef struct {
+ unsigned reg;
+ TCGv val;
+} DisasContextTemp;
+
+#define MAX_WRITEBACK 4
+
+/* This is the state at translation time. */
+typedef struct {
+ uint64_t pc; /* Current pc */
+
+ TCGv zero; /* For zero register */
+
+ DisasContextTemp wb[MAX_WRITEBACK];
+ int num_wb;
+ int mmuidx;
+ bool exit_tb;
+
+ struct {
+ TCGCond cond; /* branch condition */
+ TCGv dest; /* branch destination */
+ TCGv val1; /* value to be compared against zero, for cond */
+ } jmp; /* Jump object, only once in each TB block */
+} DisasContext;
+
+#include "exec/gen-icount.h"
+
+/* Differentiate the various pipe encodings. */
+#define TY_X0 0
+#define TY_X1 1
+#define TY_Y0 2
+#define TY_Y1 3
+
+/* Remerge the base opcode and extension fields for switching.
+ The X opcode fields are 3 bits; Y0/Y1 opcode fields are 4 bits;
+ Y2 opcode field is 2 bits. */
+#define OE(OP, EXT, XY) (TY_##XY + OP * 4 + EXT * 64)
+
+/* Similar, but for Y2 only. */
+#define OEY2(OP, MODE) (OP + MODE * 4)
+
+/* Similar, but make sure opcode names match up. */
+#define OE_RR_X0(E) OE(RRR_0_OPCODE_X0, E##_UNARY_OPCODE_X0, X0)
+#define OE_RR_X1(E) OE(RRR_0_OPCODE_X1, E##_UNARY_OPCODE_X1, X1)
+#define OE_RR_Y0(E) OE(RRR_1_OPCODE_Y0, E##_UNARY_OPCODE_Y0, Y0)
+#define OE_RR_Y1(E) OE(RRR_1_OPCODE_Y1, E##_UNARY_OPCODE_Y1, Y1)
+#define OE_RRR(E,N,XY) OE(RRR_##N##_OPCODE_##XY, E##_RRR_##N##_OPCODE_##XY, XY)
+#define OE_IM(E,XY) OE(IMM8_OPCODE_##XY, E##_IMM8_OPCODE_##XY, XY)
+#define OE_SH(E,XY) OE(SHIFT_OPCODE_##XY, E##_SHIFT_OPCODE_##XY, XY)
+
+
+static void gen_exception(DisasContext *dc, TileExcp num)
+{
+ TCGv_i32 tmp;
+
+ tcg_gen_movi_tl(cpu_pc, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
+
+ tmp = tcg_const_i32(num);
+ gen_helper_exception(cpu_env, tmp);
+ tcg_temp_free_i32(tmp);
+ dc->exit_tb = true;
+}
+
+static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
+ unsigned dest, unsigned srca)
+{
+ const char *mnemonic;
+
+ /* Eliminate nops before doing anything else. */
+ switch (opext) {
+ case OE_RR_Y0(NOP):
+ case OE_RR_Y1(NOP):
+ case OE_RR_X0(NOP):
+ case OE_RR_X1(NOP):
+ mnemonic = "nop";
+ goto do_nop;
+ case OE_RR_Y0(FNOP):
+ case OE_RR_Y1(FNOP):
+ case OE_RR_X0(FNOP):
+ case OE_RR_X1(FNOP):
+ mnemonic = "fnop";
+ do_nop:
+ if (srca || dest) {
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ }
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
+ return TILEGX_EXCP_NONE;
+ }
+
+ switch (opext) {
+ case OE_RR_X0(CNTLZ):
+ case OE_RR_Y0(CNTLZ):
+ case OE_RR_X0(CNTTZ):
+ case OE_RR_Y0(CNTTZ):
+ case OE_RR_X1(DRAIN):
+ case OE_RR_X1(DTLBPR):
+ case OE_RR_X1(FINV):
+ case OE_RR_X1(FLUSHWB):
+ case OE_RR_X1(FLUSH):
+ case OE_RR_X0(FSINGLE_PACK1):
+ case OE_RR_Y0(FSINGLE_PACK1):
+ case OE_RR_X1(ICOH):
+ case OE_RR_X1(ILL):
+ case OE_RR_Y1(ILL):
+ case OE_RR_X1(INV):
+ case OE_RR_X1(IRET):
+ case OE_RR_X1(JALRP):
+ case OE_RR_Y1(JALRP):
+ case OE_RR_X1(JALR):
+ case OE_RR_Y1(JALR):
+ case OE_RR_X1(JRP):
+ case OE_RR_Y1(JRP):
+ case OE_RR_X1(JR):
+ case OE_RR_Y1(JR):
+ case OE_RR_X1(LD1S):
+ case OE_RR_X1(LD1U):
+ case OE_RR_X1(LD2S):
+ case OE_RR_X1(LD2U):
+ case OE_RR_X1(LD4S):
+ case OE_RR_X1(LD4U):
+ case OE_RR_X1(LDNA):
+ case OE_RR_X1(LDNT1S):
+ case OE_RR_X1(LDNT1U):
+ case OE_RR_X1(LDNT2S):
+ case OE_RR_X1(LDNT2U):
+ case OE_RR_X1(LDNT4S):
+ case OE_RR_X1(LDNT4U):
+ case OE_RR_X1(LDNT):
+ case OE_RR_X1(LD):
+ case OE_RR_X1(LNK):
+ case OE_RR_Y1(LNK):
+ case OE_RR_X1(MF):
+ case OE_RR_X1(NAP):
+ case OE_RR_X0(PCNT):
+ case OE_RR_Y0(PCNT):
+ case OE_RR_X0(REVBITS):
+ case OE_RR_Y0(REVBITS):
+ case OE_RR_X0(REVBYTES):
+ case OE_RR_Y0(REVBYTES):
+ case OE_RR_X1(SWINT0):
+ case OE_RR_X1(SWINT1):
+ case OE_RR_X1(SWINT2):
+ case OE_RR_X1(SWINT3):
+ case OE_RR_X0(TBLIDXB0):
+ case OE_RR_Y0(TBLIDXB0):
+ case OE_RR_X0(TBLIDXB1):
+ case OE_RR_Y0(TBLIDXB1):
+ case OE_RR_X0(TBLIDXB2):
+ case OE_RR_Y0(TBLIDXB2):
+ case OE_RR_X0(TBLIDXB3):
+ case OE_RR_Y0(TBLIDXB3):
+ case OE_RR_X1(WH64):
+ default:
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ }
+
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
+ reg_names[dest], reg_names[srca]);
+ return TILEGX_EXCP_NONE;
+}
+
+static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
+ unsigned dest, unsigned srca, unsigned srcb)
+{
+ const char *mnemonic;
+
+ switch (opext) {
+ case OE_RRR(ADDXSC, 0, X0):
+ case OE_RRR(ADDXSC, 0, X1):
+ case OE_RRR(ADDX, 0, X0):
+ case OE_RRR(ADDX, 0, X1):
+ case OE_RRR(ADDX, 0, Y0):
+ case OE_RRR(ADDX, 0, Y1):
+ case OE_RRR(ADD, 0, X0):
+ case OE_RRR(ADD, 0, X1):
+ case OE_RRR(ADD, 0, Y0):
+ case OE_RRR(ADD, 0, Y1):
+ case OE_RRR(AND, 0, X0):
+ case OE_RRR(AND, 0, X1):
+ case OE_RRR(AND, 5, Y0):
+ case OE_RRR(AND, 5, Y1):
+ case OE_RRR(CMOVEQZ, 0, X0):
+ case OE_RRR(CMOVEQZ, 4, Y0):
+ case OE_RRR(CMOVNEZ, 0, X0):
+ case OE_RRR(CMOVNEZ, 4, Y0):
+ case OE_RRR(CMPEQ, 0, X0):
+ case OE_RRR(CMPEQ, 0, X1):
+ case OE_RRR(CMPEQ, 3, Y0):
+ case OE_RRR(CMPEQ, 3, Y1):
+ case OE_RRR(CMPEXCH4, 0, X1):
+ case OE_RRR(CMPEXCH, 0, X1):
+ case OE_RRR(CMPLES, 0, X0):
+ case OE_RRR(CMPLES, 0, X1):
+ case OE_RRR(CMPLES, 2, Y0):
+ case OE_RRR(CMPLES, 2, Y1):
+ case OE_RRR(CMPLEU, 0, X0):
+ case OE_RRR(CMPLEU, 0, X1):
+ case OE_RRR(CMPLEU, 2, Y0):
+ case OE_RRR(CMPLEU, 2, Y1):
+ case OE_RRR(CMPLTS, 0, X0):
+ case OE_RRR(CMPLTS, 0, X1):
+ case OE_RRR(CMPLTS, 2, Y0):
+ case OE_RRR(CMPLTS, 2, Y1):
+ case OE_RRR(CMPLTU, 0, X0):
+ case OE_RRR(CMPLTU, 0, X1):
+ case OE_RRR(CMPLTU, 2, Y0):
+ case OE_RRR(CMPLTU, 2, Y1):
+ case OE_RRR(CMPNE, 0, X0):
+ case OE_RRR(CMPNE, 0, X1):
+ case OE_RRR(CMPNE, 3, Y0):
+ case OE_RRR(CMPNE, 3, Y1):
+ case OE_RRR(CMULAF, 0, X0):
+ case OE_RRR(CMULA, 0, X0):
+ case OE_RRR(CMULFR, 0, X0):
+ case OE_RRR(CMULF, 0, X0):
+ case OE_RRR(CMULHR, 0, X0):
+ case OE_RRR(CMULH, 0, X0):
+ case OE_RRR(CMUL, 0, X0):
+ case OE_RRR(CRC32_32, 0, X0):
+ case OE_RRR(CRC32_8, 0, X0):
+ case OE_RRR(DBLALIGN2, 0, X0):
+ case OE_RRR(DBLALIGN2, 0, X1):
+ case OE_RRR(DBLALIGN4, 0, X0):
+ case OE_RRR(DBLALIGN4, 0, X1):
+ case OE_RRR(DBLALIGN6, 0, X0):
+ case OE_RRR(DBLALIGN6, 0, X1):
+ case OE_RRR(DBLALIGN, 0, X0):
+ case OE_RRR(EXCH4, 0, X1):
+ case OE_RRR(EXCH, 0, X1):
+ case OE_RRR(FDOUBLE_ADDSUB, 0, X0):
+ case OE_RRR(FDOUBLE_ADD_FLAGS, 0, X0):
+ case OE_RRR(FDOUBLE_MUL_FLAGS, 0, X0):
+ case OE_RRR(FDOUBLE_PACK1, 0, X0):
+ case OE_RRR(FDOUBLE_PACK2, 0, X0):
+ case OE_RRR(FDOUBLE_SUB_FLAGS, 0, X0):
+ case OE_RRR(FDOUBLE_UNPACK_MAX, 0, X0):
+ case OE_RRR(FDOUBLE_UNPACK_MIN, 0, X0):
+ case OE_RRR(FETCHADD4, 0, X1):
+ case OE_RRR(FETCHADDGEZ4, 0, X1):
+ case OE_RRR(FETCHADDGEZ, 0, X1):
+ case OE_RRR(FETCHADD, 0, X1):
+ case OE_RRR(FETCHAND4, 0, X1):
+ case OE_RRR(FETCHAND, 0, X1):
+ case OE_RRR(FETCHOR4, 0, X1):
+ case OE_RRR(FETCHOR, 0, X1):
+ case OE_RRR(FSINGLE_ADD1, 0, X0):
+ case OE_RRR(FSINGLE_ADDSUB2, 0, X0):
+ case OE_RRR(FSINGLE_MUL1, 0, X0):
+ case OE_RRR(FSINGLE_MUL2, 0, X0):
+ case OE_RRR(FSINGLE_PACK2, 0, X0):
+ case OE_RRR(FSINGLE_SUB1, 0, X0):
+ case OE_RRR(MNZ, 0, X0):
+ case OE_RRR(MNZ, 0, X1):
+ case OE_RRR(MNZ, 4, Y0):
+ case OE_RRR(MNZ, 4, Y1):
+ case OE_RRR(MULAX, 0, X0):
+ case OE_RRR(MULAX, 3, Y0):
+ case OE_RRR(MULA_HS_HS, 0, X0):
+ case OE_RRR(MULA_HS_HS, 9, Y0):
+ case OE_RRR(MULA_HS_HU, 0, X0):
+ case OE_RRR(MULA_HS_LS, 0, X0):
+ case OE_RRR(MULA_HS_LU, 0, X0):
+ case OE_RRR(MULA_HU_HU, 0, X0):
+ case OE_RRR(MULA_HU_HU, 9, Y0):
+ case OE_RRR(MULA_HU_LS, 0, X0):
+ case OE_RRR(MULA_HU_LU, 0, X0):
+ case OE_RRR(MULA_LS_LS, 0, X0):
+ case OE_RRR(MULA_LS_LS, 9, Y0):
+ case OE_RRR(MULA_LS_LU, 0, X0):
+ case OE_RRR(MULA_LU_LU, 0, X0):
+ case OE_RRR(MULA_LU_LU, 9, Y0):
+ case OE_RRR(MULX, 0, X0):
+ case OE_RRR(MULX, 3, Y0):
+ case OE_RRR(MUL_HS_HS, 0, X0):
+ case OE_RRR(MUL_HS_HS, 8, Y0):
+ case OE_RRR(MUL_HS_HU, 0, X0):
+ case OE_RRR(MUL_HS_LS, 0, X0):
+ case OE_RRR(MUL_HS_LU, 0, X0):
+ case OE_RRR(MUL_HU_HU, 0, X0):
+ case OE_RRR(MUL_HU_HU, 8, Y0):
+ case OE_RRR(MUL_HU_LS, 0, X0):
+ case OE_RRR(MUL_HU_LU, 0, X0):
+ case OE_RRR(MUL_LS_LS, 0, X0):
+ case OE_RRR(MUL_LS_LS, 8, Y0):
+ case OE_RRR(MUL_LS_LU, 0, X0):
+ case OE_RRR(MUL_LU_LU, 0, X0):
+ case OE_RRR(MUL_LU_LU, 8, Y0):
+ case OE_RRR(MZ, 0, X0):
+ case OE_RRR(MZ, 0, X1):
+ case OE_RRR(MZ, 4, Y0):
+ case OE_RRR(MZ, 4, Y1):
+ case OE_RRR(NOR, 0, X0):
+ case OE_RRR(NOR, 0, X1):
+ case OE_RRR(NOR, 5, Y0):
+ case OE_RRR(NOR, 5, Y1):
+ case OE_RRR(OR, 0, X0):
+ case OE_RRR(OR, 0, X1):
+ case OE_RRR(OR, 5, Y0):
+ case OE_RRR(OR, 5, Y1):
+ case OE_RRR(ROTL, 0, X0):
+ case OE_RRR(ROTL, 0, X1):
+ case OE_RRR(ROTL, 6, Y0):
+ case OE_RRR(ROTL, 6, Y1):
+ case OE_RRR(SHL1ADDX, 0, X0):
+ case OE_RRR(SHL1ADDX, 0, X1):
+ case OE_RRR(SHL1ADDX, 7, Y0):
+ case OE_RRR(SHL1ADDX, 7, Y1):
+ case OE_RRR(SHL1ADD, 0, X0):
+ case OE_RRR(SHL1ADD, 0, X1):
+ case OE_RRR(SHL1ADD, 1, Y0):
+ case OE_RRR(SHL1ADD, 1, Y1):
+ case OE_RRR(SHL2ADDX, 0, X0):
+ case OE_RRR(SHL2ADDX, 0, X1):
+ case OE_RRR(SHL2ADDX, 7, Y0):
+ case OE_RRR(SHL2ADDX, 7, Y1):
+ case OE_RRR(SHL2ADD, 0, X0):
+ case OE_RRR(SHL2ADD, 0, X1):
+ case OE_RRR(SHL2ADD, 1, Y0):
+ case OE_RRR(SHL2ADD, 1, Y1):
+ case OE_RRR(SHL3ADDX, 0, X0):
+ case OE_RRR(SHL3ADDX, 0, X1):
+ case OE_RRR(SHL3ADDX, 7, Y0):
+ case OE_RRR(SHL3ADDX, 7, Y1):
+ case OE_RRR(SHL3ADD, 0, X0):
+ case OE_RRR(SHL3ADD, 0, X1):
+ case OE_RRR(SHL3ADD, 1, Y0):
+ case OE_RRR(SHL3ADD, 1, Y1):
+ case OE_RRR(SHLX, 0, X0):
+ case OE_RRR(SHLX, 0, X1):
+ case OE_RRR(SHL, 0, X0):
+ case OE_RRR(SHL, 0, X1):
+ case OE_RRR(SHL, 6, Y0):
+ case OE_RRR(SHL, 6, Y1):
+ case OE_RRR(SHRS, 0, X0):
+ case OE_RRR(SHRS, 0, X1):
+ case OE_RRR(SHRS, 6, Y0):
+ case OE_RRR(SHRS, 6, Y1):
+ case OE_RRR(SHRUX, 0, X0):
+ case OE_RRR(SHRUX, 0, X1):
+ case OE_RRR(SHRU, 0, X0):
+ case OE_RRR(SHRU, 0, X1):
+ case OE_RRR(SHRU, 6, Y0):
+ case OE_RRR(SHRU, 6, Y1):
+ case OE_RRR(SHUFFLEBYTES, 0, X0):
+ case OE_RRR(ST1, 0, X1):
+ case OE_RRR(ST2, 0, X1):
+ case OE_RRR(ST4, 0, X1):
+ case OE_RRR(STNT1, 0, X1):
+ case OE_RRR(STNT2, 0, X1):
+ case OE_RRR(STNT4, 0, X1):
+ case OE_RRR(STNT, 0, X1):
+ case OE_RRR(ST, 0, X1):
+ case OE_RRR(SUBXSC, 0, X0):
+ case OE_RRR(SUBXSC, 0, X1):
+ case OE_RRR(SUBX, 0, X0):
+ case OE_RRR(SUBX, 0, X1):
+ case OE_RRR(SUBX, 0, Y0):
+ case OE_RRR(SUBX, 0, Y1):
+ case OE_RRR(SUB, 0, X0):
+ case OE_RRR(SUB, 0, X1):
+ case OE_RRR(SUB, 0, Y0):
+ case OE_RRR(SUB, 0, Y1):
+ case OE_RRR(V1ADDUC, 0, X0):
+ case OE_RRR(V1ADDUC, 0, X1):
+ case OE_RRR(V1ADD, 0, X0):
+ case OE_RRR(V1ADD, 0, X1):
+ case OE_RRR(V1ADIFFU, 0, X0):
+ case OE_RRR(V1AVGU, 0, X0):
+ case OE_RRR(V1CMPEQ, 0, X0):
+ case OE_RRR(V1CMPEQ, 0, X1):
+ case OE_RRR(V1CMPLES, 0, X0):
+ case OE_RRR(V1CMPLES, 0, X1):
+ case OE_RRR(V1CMPLEU, 0, X0):
+ case OE_RRR(V1CMPLEU, 0, X1):
+ case OE_RRR(V1CMPLTS, 0, X0):
+ case OE_RRR(V1CMPLTS, 0, X1):
+ case OE_RRR(V1CMPLTU, 0, X0):
+ case OE_RRR(V1CMPLTU, 0, X1):
+ case OE_RRR(V1CMPNE, 0, X0):
+ case OE_RRR(V1CMPNE, 0, X1):
+ case OE_RRR(V1DDOTPUA, 0, X0):
+ case OE_RRR(V1DDOTPUSA, 0, X0):
+ case OE_RRR(V1DDOTPUS, 0, X0):
+ case OE_RRR(V1DDOTPU, 0, X0):
+ case OE_RRR(V1DOTPA, 0, X0):
+ case OE_RRR(V1DOTPUA, 0, X0):
+ case OE_RRR(V1DOTPUSA, 0, X0):
+ case OE_RRR(V1DOTPUS, 0, X0):
+ case OE_RRR(V1DOTPU, 0, X0):
+ case OE_RRR(V1DOTP, 0, X0):
+ case OE_RRR(V1INT_H, 0, X0):
+ case OE_RRR(V1INT_H, 0, X1):
+ case OE_RRR(V1INT_L, 0, X0):
+ case OE_RRR(V1INT_L, 0, X1):
+ case OE_RRR(V1MAXU, 0, X0):
+ case OE_RRR(V1MAXU, 0, X1):
+ case OE_RRR(V1MINU, 0, X0):
+ case OE_RRR(V1MINU, 0, X1):
+ case OE_RRR(V1MNZ, 0, X0):
+ case OE_RRR(V1MNZ, 0, X1):
+ case OE_RRR(V1MULTU, 0, X0):
+ case OE_RRR(V1MULUS, 0, X0):
+ case OE_RRR(V1MULU, 0, X0):
+ case OE_RRR(V1MZ, 0, X0):
+ case OE_RRR(V1MZ, 0, X1):
+ case OE_RRR(V1SADAU, 0, X0):
+ case OE_RRR(V1SADU, 0, X0):
+ case OE_RRR(V1SHL, 0, X0):
+ case OE_RRR(V1SHL, 0, X1):
+ case OE_RRR(V1SHRS, 0, X0):
+ case OE_RRR(V1SHRS, 0, X1):
+ case OE_RRR(V1SHRU, 0, X0):
+ case OE_RRR(V1SHRU, 0, X1):
+ case OE_RRR(V1SUBUC, 0, X0):
+ case OE_RRR(V1SUBUC, 0, X1):
+ case OE_RRR(V1SUB, 0, X0):
+ case OE_RRR(V1SUB, 0, X1):
+ case OE_RRR(V2ADDSC, 0, X0):
+ case OE_RRR(V2ADDSC, 0, X1):
+ case OE_RRR(V2ADD, 0, X0):
+ case OE_RRR(V2ADD, 0, X1):
+ case OE_RRR(V2ADIFFS, 0, X0):
+ case OE_RRR(V2AVGS, 0, X0):
+ case OE_RRR(V2CMPEQ, 0, X0):
+ case OE_RRR(V2CMPEQ, 0, X1):
+ case OE_RRR(V2CMPLES, 0, X0):
+ case OE_RRR(V2CMPLES, 0, X1):
+ case OE_RRR(V2CMPLEU, 0, X0):
+ case OE_RRR(V2CMPLEU, 0, X1):
+ case OE_RRR(V2CMPLTS, 0, X0):
+ case OE_RRR(V2CMPLTS, 0, X1):
+ case OE_RRR(V2CMPLTU, 0, X0):
+ case OE_RRR(V2CMPLTU, 0, X1):
+ case OE_RRR(V2CMPNE, 0, X0):
+ case OE_RRR(V2CMPNE, 0, X1):
+ case OE_RRR(V2DOTPA, 0, X0):
+ case OE_RRR(V2DOTP, 0, X0):
+ case OE_RRR(V2INT_H, 0, X0):
+ case OE_RRR(V2INT_H, 0, X1):
+ case OE_RRR(V2INT_L, 0, X0):
+ case OE_RRR(V2INT_L, 0, X1):
+ case OE_RRR(V2MAXS, 0, X0):
+ case OE_RRR(V2MAXS, 0, X1):
+ case OE_RRR(V2MINS, 0, X0):
+ case OE_RRR(V2MINS, 0, X1):
+ case OE_RRR(V2MNZ, 0, X0):
+ case OE_RRR(V2MNZ, 0, X1):
+ case OE_RRR(V2MULFSC, 0, X0):
+ case OE_RRR(V2MULS, 0, X0):
+ case OE_RRR(V2MULTS, 0, X0):
+ case OE_RRR(V2MZ, 0, X0):
+ case OE_RRR(V2MZ, 0, X1):
+ case OE_RRR(V2PACKH, 0, X0):
+ case OE_RRR(V2PACKH, 0, X1):
+ case OE_RRR(V2PACKL, 0, X0):
+ case OE_RRR(V2PACKL, 0, X1):
+ case OE_RRR(V2PACKUC, 0, X0):
+ case OE_RRR(V2PACKUC, 0, X1):
+ case OE_RRR(V2SADAS, 0, X0):
+ case OE_RRR(V2SADAU, 0, X0):
+ case OE_RRR(V2SADS, 0, X0):
+ case OE_RRR(V2SADU, 0, X0):
+ case OE_RRR(V2SHLSC, 0, X0):
+ case OE_RRR(V2SHLSC, 0, X1):
+ case OE_RRR(V2SHL, 0, X0):
+ case OE_RRR(V2SHL, 0, X1):
+ case OE_RRR(V2SHRS, 0, X0):
+ case OE_RRR(V2SHRS, 0, X1):
+ case OE_RRR(V2SHRU, 0, X0):
+ case OE_RRR(V2SHRU, 0, X1):
+ case OE_RRR(V2SUBSC, 0, X0):
+ case OE_RRR(V2SUBSC, 0, X1):
+ case OE_RRR(V2SUB, 0, X0):
+ case OE_RRR(V2SUB, 0, X1):
+ case OE_RRR(V4ADDSC, 0, X0):
+ case OE_RRR(V4ADDSC, 0, X1):
+ case OE_RRR(V4ADD, 0, X0):
+ case OE_RRR(V4ADD, 0, X1):
+ case OE_RRR(V4INT_H, 0, X0):
+ case OE_RRR(V4INT_H, 0, X1):
+ case OE_RRR(V4INT_L, 0, X0):
+ case OE_RRR(V4INT_L, 0, X1):
+ case OE_RRR(V4PACKSC, 0, X0):
+ case OE_RRR(V4PACKSC, 0, X1):
+ case OE_RRR(V4SHLSC, 0, X0):
+ case OE_RRR(V4SHLSC, 0, X1):
+ case OE_RRR(V4SHL, 0, X0):
+ case OE_RRR(V4SHL, 0, X1):
+ case OE_RRR(V4SHRS, 0, X0):
+ case OE_RRR(V4SHRS, 0, X1):
+ case OE_RRR(V4SHRU, 0, X0):
+ case OE_RRR(V4SHRU, 0, X1):
+ case OE_RRR(V4SUBSC, 0, X0):
+ case OE_RRR(V4SUBSC, 0, X1):
+ case OE_RRR(V4SUB, 0, X0):
+ case OE_RRR(V4SUB, 0, X1):
+ case OE_RRR(XOR, 0, X0):
+ case OE_RRR(XOR, 0, X1):
+ case OE_RRR(XOR, 5, Y0):
+ case OE_RRR(XOR, 5, Y1):
+ default:
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ }
+
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %s", mnemonic,
+ reg_names[dest], reg_names[srca], reg_names[srcb]);
+ return TILEGX_EXCP_NONE;
+}
+
+static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
+ unsigned dest, unsigned srca, int imm)
+{
+ const char *mnemonic;
+
+ switch (opext) {
+ case OE_IM(ADDI, X0):
+ case OE_IM(ADDI, X1):
+ case OE_IM(ADDXI, X0):
+ case OE_IM(ADDXI, X1):
+ case OE_IM(ANDI, X0):
+ case OE_IM(ANDI, X1):
+ case OE_IM(CMPEQI, X0):
+ case OE_IM(CMPEQI, X1):
+ case OE_IM(CMPLTSI, X0):
+ case OE_IM(CMPLTSI, X1):
+ case OE_IM(CMPLTUI, X0):
+ case OE_IM(CMPLTUI, X1):
+ case OE_IM(LD1S_ADD, X1):
+ case OE_IM(LD1U_ADD, X1):
+ case OE_IM(LD2S_ADD, X1):
+ case OE_IM(LD2U_ADD, X1):
+ case OE_IM(LD4S_ADD, X1):
+ case OE_IM(LD4U_ADD, X1):
+ case OE_IM(LDNT1S_ADD, X1):
+ case OE_IM(LDNT1U_ADD, X1):
+ case OE_IM(LDNT2S_ADD, X1):
+ case OE_IM(LDNT2U_ADD, X1):
+ case OE_IM(LDNT4S_ADD, X1):
+ case OE_IM(LDNT4U_ADD, X1):
+ case OE_IM(LDNT_ADD, X1):
+ case OE_IM(LD_ADD, X1):
+ case OE_IM(LWNA_ADD, X1):
+ case OE_IM(MFSPR, X1):
+ case OE_IM(MTSPR, X1):
+ case OE_IM(ORI, X0):
+ case OE_IM(ORI, X1):
+ case OE_IM(ST1_ADD, X1):
+ case OE_IM(ST2_ADD, X1):
+ case OE_IM(ST4_ADD, X1):
+ case OE_IM(STNT1_ADD, X1):
+ case OE_IM(STNT2_ADD, X1):
+ case OE_IM(STNT4_ADD, X1):
+ case OE_IM(STNT_ADD, X1):
+ case OE_IM(ST_ADD, X1):
+ case OE_IM(V1ADDI, X0):
+ case OE_IM(V1ADDI, X1):
+ case OE_IM(V1CMPEQI, X0):
+ case OE_IM(V1CMPEQI, X1):
+ case OE_IM(V1CMPLTSI, X0):
+ case OE_IM(V1CMPLTSI, X1):
+ case OE_IM(V1CMPLTUI, X0):
+ case OE_IM(V1CMPLTUI, X1):
+ case OE_IM(V1MAXUI, X0):
+ case OE_IM(V1MAXUI, X1):
+ case OE_IM(V1MINUI, X0):
+ case OE_IM(V1MINUI, X1):
+ case OE_IM(V2ADDI, X0):
+ case OE_IM(V2ADDI, X1):
+ case OE_IM(V2CMPEQI, X0):
+ case OE_IM(V2CMPEQI, X1):
+ case OE_IM(V2CMPLTSI, X0):
+ case OE_IM(V2CMPLTSI, X1):
+ case OE_IM(V2CMPLTUI, X0):
+ case OE_IM(V2CMPLTUI, X1):
+ case OE_IM(V2MAXSI, X0):
+ case OE_IM(V2MAXSI, X1):
+ case OE_IM(V2MINSI, X0):
+ case OE_IM(V2MINSI, X1):
+ case OE_IM(XORI, X0):
+ case OE_IM(XORI, X1):
+
+ case OE_SH(ROTLI, X0):
+ case OE_SH(ROTLI, X1):
+ case OE_SH(ROTLI, Y0):
+ case OE_SH(ROTLI, Y1):
+ case OE_SH(SHLI, X0):
+ case OE_SH(SHLI, X1):
+ case OE_SH(SHLI, Y0):
+ case OE_SH(SHLI, Y1):
+ case OE_SH(SHLXI, X0):
+ case OE_SH(SHLXI, X1):
+ case OE_SH(SHRSI, X0):
+ case OE_SH(SHRSI, X1):
+ case OE_SH(SHRSI, Y0):
+ case OE_SH(SHRSI, Y1):
+ case OE_SH(SHRUI, X0):
+ case OE_SH(SHRUI, X1):
+ case OE_SH(SHRUI, Y0):
+ case OE_SH(SHRUI, Y1):
+ case OE_SH(SHRUXI, X0):
+ case OE_SH(SHRUXI, X1):
+ case OE_SH(V1SHLI, X0):
+ case OE_SH(V1SHLI, X1):
+ case OE_SH(V1SHRSI, X0):
+ case OE_SH(V1SHRSI, X1):
+ case OE_SH(V1SHRUI, X0):
+ case OE_SH(V1SHRUI, X1):
+ case OE_SH(V2SHLI, X0):
+ case OE_SH(V2SHLI, X1):
+ case OE_SH(V2SHRSI, X0):
+ case OE_SH(V2SHRSI, X1):
+ case OE_SH(V2SHRUI, X0):
+ case OE_SH(V2SHRUI, X1):
+
+ case OE(ADDI_OPCODE_Y0, 0, Y0):
+ case OE(ADDI_OPCODE_Y1, 0, Y1):
+ case OE(ADDLI_OPCODE_X0, 0, X0):
+ case OE(ADDLI_OPCODE_X1, 0, X1):
+ case OE(ADDXI_OPCODE_Y0, 0, Y0):
+ case OE(ADDXI_OPCODE_Y1, 0, Y1):
+ case OE(ADDXLI_OPCODE_X0, 0, X0):
+ case OE(ADDXLI_OPCODE_X1, 0, X1):
+ case OE(ANDI_OPCODE_Y0, 0, Y0):
+ case OE(ANDI_OPCODE_Y1, 0, Y1):
+ case OE(CMPEQI_OPCODE_Y0, 0, Y0):
+ case OE(CMPEQI_OPCODE_Y1, 0, Y1):
+ case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
+ case OE(CMPLTSI_OPCODE_Y1, 0, Y1):
+ case OE(SHL16INSLI_OPCODE_X0, 0, X0):
+ case OE(SHL16INSLI_OPCODE_X1, 0, X1):
+
+ default:
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ }
+
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", mnemonic,
+ reg_names[dest], reg_names[srca], imm);
+ return TILEGX_EXCP_NONE;
+}
+
+static TileExcp gen_bf_opcode_x0(DisasContext *dc, unsigned ext,
+ unsigned dest, unsigned srca,
+ unsigned bfs, unsigned bfe)
+{
+ const char *mnemonic;
+
+ switch (ext) {
+ case BFEXTU_BF_OPCODE_X0:
+ case BFEXTS_BF_OPCODE_X0:
+ case BFINS_BF_OPCODE_X0:
+ case MM_BF_OPCODE_X0:
+ default:
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ }
+
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %u, %u", mnemonic,
+ reg_names[dest], reg_names[srca], bfs, bfe);
+ return TILEGX_EXCP_NONE;
+}
+
+static TileExcp gen_branch_opcode_x1(DisasContext *dc, unsigned ext,
+ unsigned srca, int off)
+{
+ target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
+ const char *mnemonic;
+
+ switch (ext) {
+ case BEQZT_BRANCH_OPCODE_X1:
+ case BEQZ_BRANCH_OPCODE_X1:
+ case BNEZT_BRANCH_OPCODE_X1:
+ case BNEZ_BRANCH_OPCODE_X1:
+ case BLBC_BRANCH_OPCODE_X1:
+ case BGEZT_BRANCH_OPCODE_X1:
+ case BGEZ_BRANCH_OPCODE_X1:
+ case BGTZT_BRANCH_OPCODE_X1:
+ case BGTZ_BRANCH_OPCODE_X1:
+ case BLBCT_BRANCH_OPCODE_X1:
+ case BLBST_BRANCH_OPCODE_X1:
+ case BLBS_BRANCH_OPCODE_X1:
+ case BLEZT_BRANCH_OPCODE_X1:
+ case BLEZ_BRANCH_OPCODE_X1:
+ case BLTZT_BRANCH_OPCODE_X1:
+ case BLTZ_BRANCH_OPCODE_X1:
+ default:
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ }
+
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
+ qemu_log("%s %s, " TARGET_FMT_lx " <%s>",
+ mnemonic, reg_names[srca], tgt, lookup_symbol(tgt));
+ }
+ return TILEGX_EXCP_NONE;
+}
+
+static TileExcp gen_jump_opcode_x1(DisasContext *dc, unsigned ext,
+ int off)
+{
+ target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
+ const char *mnemonic;
+
+ switch (ext) {
+ case JAL_JUMP_OPCODE_X1:
+ case J_JUMP_OPCODE_X1:
+ default:
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ }
+
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
+ qemu_log("%s " TARGET_FMT_lx " <%s>",
+ mnemonic, tgt, lookup_symbol(tgt));
+ }
+ return TILEGX_EXCP_NONE;
+}
+
+static TileExcp decode_y0(DisasContext *dc, tilegx_bundle_bits bundle)
+{
+ unsigned opc = get_Opcode_Y0(bundle);
+ unsigned ext = get_RRROpcodeExtension_Y0(bundle);
+ unsigned dest = get_Dest_Y0(bundle);
+ unsigned srca = get_SrcA_Y0(bundle);
+ unsigned srcb;
+ int imm;
+
+ switch (opc) {
+ case RRR_1_OPCODE_Y0:
+ if (ext == UNARY_RRR_1_OPCODE_Y0) {
+ ext = get_UnaryOpcodeExtension_Y0(bundle);
+ return gen_rr_opcode(dc, OE(opc, ext, Y0), dest, srca);
+ }
+ /* fallthru */
+ case RRR_0_OPCODE_Y0:
+ case RRR_2_OPCODE_Y0:
+ case RRR_3_OPCODE_Y0:
+ case RRR_4_OPCODE_Y0:
+ case RRR_5_OPCODE_Y0:
+ case RRR_6_OPCODE_Y0:
+ case RRR_7_OPCODE_Y0:
+ case RRR_8_OPCODE_Y0:
+ case RRR_9_OPCODE_Y0:
+ srcb = get_SrcB_Y0(bundle);
+ return gen_rrr_opcode(dc, OE(opc, ext, Y0), dest, srca, srcb);
+
+ case SHIFT_OPCODE_Y0:
+ ext = get_ShiftOpcodeExtension_Y0(bundle);
+ imm = get_ShAmt_Y0(bundle);
+ return gen_rri_opcode(dc, OE(opc, ext, Y0), dest, srca, imm);
+
+ case ADDI_OPCODE_Y0:
+ case ADDXI_OPCODE_Y0:
+ case ANDI_OPCODE_Y0:
+ case CMPEQI_OPCODE_Y0:
+ case CMPLTSI_OPCODE_Y0:
+ imm = (int8_t)get_Imm8_Y0(bundle);
+ return gen_rri_opcode(dc, OE(opc, 0, Y0), dest, srca, imm);
+
+ default:
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ }
+}
+
+static TileExcp decode_y1(DisasContext *dc, tilegx_bundle_bits bundle)
+{
+ unsigned opc = get_Opcode_Y1(bundle);
+ unsigned ext = get_RRROpcodeExtension_Y1(bundle);
+ unsigned dest = get_Dest_Y1(bundle);
+ unsigned srca = get_SrcA_Y1(bundle);
+ unsigned srcb;
+ int imm;
+
+ switch (get_Opcode_Y1(bundle)) {
+ case RRR_1_OPCODE_Y1:
+ if (ext == UNARY_RRR_1_OPCODE_Y0) {
+ ext = get_UnaryOpcodeExtension_Y1(bundle);
+ return gen_rr_opcode(dc, OE(opc, ext, Y1), dest, srca);
+ }
+ /* fallthru */
+ case RRR_0_OPCODE_Y1:
+ case RRR_2_OPCODE_Y1:
+ case RRR_3_OPCODE_Y1:
+ case RRR_4_OPCODE_Y1:
+ case RRR_5_OPCODE_Y1:
+ case RRR_6_OPCODE_Y1:
+ case RRR_7_OPCODE_Y1:
+ srcb = get_SrcB_Y1(bundle);
+ return gen_rrr_opcode(dc, OE(opc, ext, Y1), dest, srca, srcb);
+
+ case SHIFT_OPCODE_Y1:
+ ext = get_ShiftOpcodeExtension_Y1(bundle);
+ imm = get_ShAmt_Y1(bundle);
+ return gen_rri_opcode(dc, OE(opc, ext, Y1), dest, srca, imm);
+
+ case ADDI_OPCODE_Y1:
+ case ADDXI_OPCODE_Y1:
+ case ANDI_OPCODE_Y1:
+ case CMPEQI_OPCODE_Y1:
+ case CMPLTSI_OPCODE_Y1:
+ imm = (int8_t)get_Imm8_Y1(bundle);
+ return gen_rri_opcode(dc, OE(opc, 0, Y1), dest, srca, imm);
+
+ default:
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ }
+}
+
+static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
+{
+ unsigned mode = get_Mode(bundle);
+ unsigned opc = get_Opcode_Y2(bundle);
+ unsigned srca = get_SrcA_Y2(bundle);
+ unsigned srcbdest = get_SrcBDest_Y2(bundle);
+ const char *mnemonic;
+
+ switch (OEY2(opc, mode)) {
+ case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2):
+ case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2):
+ case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2):
+ case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2):
+ case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2):
+ case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2):
+ case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2):
+
+ case OEY2(ST1_OPCODE_Y2, MODE_OPCODE_YC2):
+ case OEY2(ST2_OPCODE_Y2, MODE_OPCODE_YC2):
+ case OEY2(ST4_OPCODE_Y2, MODE_OPCODE_YC2):
+ case OEY2(ST_OPCODE_Y2, MODE_OPCODE_YC2):
+
+ default:
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ }
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
+ reg_names[srca], reg_names[srcbdest]);
+ return TILEGX_EXCP_NONE;
+}
+
+static TileExcp decode_x0(DisasContext *dc, tilegx_bundle_bits bundle)
+{
+ unsigned opc = get_Opcode_X0(bundle);
+ unsigned dest = get_Dest_X0(bundle);
+ unsigned srca = get_SrcA_X0(bundle);
+ unsigned ext, srcb, bfs, bfe;
+ int imm;
+
+ switch (opc) {
+ case RRR_0_OPCODE_X0:
+ ext = get_RRROpcodeExtension_X0(bundle);
+ if (ext == UNARY_RRR_0_OPCODE_X0) {
+ ext = get_UnaryOpcodeExtension_X0(bundle);
+ return gen_rr_opcode(dc, OE(opc, ext, X0), dest, srca);
+ }
+ srcb = get_SrcB_X0(bundle);
+ return gen_rrr_opcode(dc, OE(opc, ext, X0), dest, srca, srcb);
+
+ case SHIFT_OPCODE_X0:
+ ext = get_ShiftOpcodeExtension_X0(bundle);
+ imm = get_ShAmt_X0(bundle);
+ return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
+
+ case IMM8_OPCODE_X0:
+ ext = get_Imm8OpcodeExtension_X0(bundle);
+ imm = (int8_t)get_Imm8_X0(bundle);
+ return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
+
+ case BF_OPCODE_X0:
+ ext = get_BFOpcodeExtension_X0(bundle);
+ bfs = get_BFStart_X0(bundle);
+ bfe = get_BFEnd_X0(bundle);
+ return gen_bf_opcode_x0(dc, ext, dest, srca, bfs, bfe);
+
+ case ADDLI_OPCODE_X0:
+ case SHL16INSLI_OPCODE_X0:
+ case ADDXLI_OPCODE_X0:
+ imm = (int16_t)get_Imm16_X0(bundle);
+ return gen_rri_opcode(dc, OE(opc, 0, X0), dest, srca, imm);
+
+ default:
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ }
+}
+
+static TileExcp decode_x1(DisasContext *dc, tilegx_bundle_bits bundle)
+{
+ unsigned opc = get_Opcode_X1(bundle);
+ unsigned dest = get_Dest_X1(bundle);
+ unsigned srca = get_SrcA_X1(bundle);
+ unsigned ext, srcb;
+ int imm;
+
+ switch (opc) {
+ case RRR_0_OPCODE_X1:
+ ext = get_RRROpcodeExtension_X1(bundle);
+ if (ext == UNARY_RRR_0_OPCODE_X1) {
+ ext = get_UnaryOpcodeExtension_X1(bundle);
+ return gen_rr_opcode(dc, OE(opc, ext, X1), dest, srca);
+ }
+ srcb = get_SrcB_X1(bundle);
+ return gen_rrr_opcode(dc, OE(opc, ext, X1), dest, srca, srcb);
+
+ case SHIFT_OPCODE_X1:
+ ext = get_ShiftOpcodeExtension_X1(bundle);
+ imm = get_ShAmt_X1(bundle);
+ return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
+
+ case IMM8_OPCODE_X1:
+ ext = get_Imm8OpcodeExtension_X1(bundle);
+ imm = (int8_t)get_Imm8_X1(bundle);
+ return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
+
+ case BRANCH_OPCODE_X1:
+ ext = get_BrType_X1(bundle);
+ imm = sextract32(get_BrOff_X1(bundle), 0, 17);
+ return gen_branch_opcode_x1(dc, ext, srca, imm);
+
+ case JUMP_OPCODE_X1:
+ ext = get_JumpOpcodeExtension_X1(bundle);
+ imm = sextract32(get_JumpOff_X1(bundle), 0, 27);
+ return gen_jump_opcode_x1(dc, ext, imm);
+
+ case ADDLI_OPCODE_X1:
+ case SHL16INSLI_OPCODE_X1:
+ case ADDXLI_OPCODE_X1:
+ imm = (int16_t)get_Imm16_X1(bundle);
+ return gen_rri_opcode(dc, OE(opc, 0, X1), dest, srca, imm);
+
+ default:
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ }
+}
+
+static void notice_excp(DisasContext *dc, uint64_t bundle,
+ const char *type, TileExcp excp)
+{
+ if (likely(excp == TILEGX_EXCP_NONE)) {
+ return;
+ }
+ gen_exception(dc, excp);
+ if (excp == TILEGX_EXCP_OPCODE_UNIMPLEMENTED) {
+ qemu_log_mask(LOG_UNIMP, "UNIMP %s, [" FMT64X "]\n", type, bundle);
+ }
+}
+
+static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(dc->wb); i++) {
+ DisasContextTemp *wb = &dc->wb[i];
+ wb->reg = TILEGX_R_NOREG;
+ TCGV_UNUSED_I64(wb->val);
+ }
+ dc->num_wb = 0;
+
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
+ tcg_gen_debug_insn_start(dc->pc);
+ }
+
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, " %" PRIx64 ": { ", dc->pc);
+ if (get_Mode(bundle)) {
+ notice_excp(dc, bundle, "y0", decode_y0(dc, bundle));
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
+ notice_excp(dc, bundle, "y1", decode_y1(dc, bundle));
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
+ notice_excp(dc, bundle, "y2", decode_y2(dc, bundle));
+ } else {
+ notice_excp(dc, bundle, "x0", decode_x0(dc, bundle));
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
+ notice_excp(dc, bundle, "x1", decode_x1(dc, bundle));
+ }
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, " }\n");
+
+ for (i = dc->num_wb - 1; i >= 0; --i) {
+ DisasContextTemp *wb = &dc->wb[i];
+ if (wb->reg < TILEGX_R_COUNT) {
+ tcg_gen_mov_i64(cpu_regs[wb->reg], wb->val);
+ }
+ tcg_temp_free_i64(wb->val);
+ }
+
+ if (dc->jmp.cond != TCG_COND_NEVER) {
+ if (dc->jmp.cond == TCG_COND_ALWAYS) {
+ tcg_gen_mov_i64(cpu_pc, dc->jmp.dest);
+ } else {
+ TCGv next = tcg_const_i64(dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
+ tcg_gen_movcond_i64(dc->jmp.cond, cpu_pc,
+ dc->jmp.val1, load_zero(dc),
+ dc->jmp.dest, next);
+ tcg_temp_free_i64(dc->jmp.val1);
+ tcg_temp_free_i64(next);
+ }
+ tcg_temp_free_i64(dc->jmp.dest);
+ tcg_gen_exit_tb(0);
+ dc->exit_tb = true;
+ }
+}
+
+static inline void gen_intermediate_code_internal(TileGXCPU *cpu,
+ TranslationBlock *tb,
+ bool search_pc)
+{
+ DisasContext ctx;
+ DisasContext *dc = &ctx;
+ CPUState *cs = CPU(cpu);
+ CPUTLGState *env = &cpu->env;
+ uint64_t pc_start = tb->pc;
+ uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
+ int j, lj = -1;
+ int num_insns = 0;
+ int max_insns = tb->cflags & CF_COUNT_MASK;
+
+ dc->pc = pc_start;
+ dc->mmuidx = 0;
+ dc->exit_tb = false;
+ dc->jmp.cond = TCG_COND_NEVER;
+ TCGV_UNUSED_I64(dc->jmp.dest);
+ TCGV_UNUSED_I64(dc->jmp.val1);
+ TCGV_UNUSED_I64(dc->jmp.val2);
+ TCGV_UNUSED_I64(dc->zero);
+
+ if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
+ qemu_log("IN: %s\n", lookup_symbol(pc_start));
+ }
+ if (!max_insns) {
+ max_insns = CF_COUNT_MASK;
+ }
+ if (cs->singlestep_enabled || singlestep) {
+ max_insns = 1;
+ }
+ gen_tb_start(tb);
+
+ while (1) {
+ if (search_pc) {
+ j = tcg_op_buf_count();
+ if (lj < j) {
+ lj++;
+ while (lj < j) {
+ tcg_ctx.gen_opc_instr_start[lj++] = 0;
+ }
+ }
+ tcg_ctx.gen_opc_pc[lj] = dc->pc;
+ tcg_ctx.gen_opc_instr_start[lj] = 1;
+ tcg_ctx.gen_opc_icount[lj] = num_insns;
+ }
+ translate_one_bundle(dc, cpu_ldq_data(env, dc->pc));
+
+ if (dc->exit_tb) {
+ /* PC updated and EXIT_TB/GOTO_TB/exception emitted. */
+ break;
+ }
+ dc->pc += TILEGX_BUNDLE_SIZE_IN_BYTES;
+ if (++num_insns >= max_insns
+ || dc->pc >= next_page_start
+ || tcg_op_buf_full()) {
+ /* Ending the TB due to TB size or page boundary. Set PC. */
+ tcg_gen_movi_tl(cpu_pc, dc->pc);
+ tcg_gen_exit_tb(0);
+ break;
+ }
+ }
+
+ gen_tb_end(tb, num_insns);
+ if (search_pc) {
+ j = tcg_op_buf_count();
+ lj++;
+ while (lj <= j) {
+ tcg_ctx.gen_opc_instr_start[lj++] = 0;
+ }
+ } else {
+ tb->size = dc->pc - pc_start;
+ tb->icount = num_insns;
+ }
+
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
+}
+
+void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
+{
+ gen_intermediate_code_internal(tilegx_env_get_cpu(env), tb, false);
+}
+
+void gen_intermediate_code_pc(CPUTLGState *env, struct TranslationBlock *tb)
+{
+ gen_intermediate_code_internal(tilegx_env_get_cpu(env), tb, true);
+}
+
+void restore_state_to_opc(CPUTLGState *env, TranslationBlock *tb, int pc_pos)
+{
+ env->pc = tcg_ctx.gen_opc_pc[pc_pos];
+}
+
+void tilegx_tcg_init(void)
+{
+ int i;
+
+ cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
+ cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUTLGState, pc), "pc");
+ for (i = 0; i < TILEGX_R_COUNT; i++) {
+ cpu_regs[i] = tcg_global_mem_new_i64(TCG_AREG0,
+ offsetof(CPUTLGState, regs[i]),
+ reg_names[i]);
+ }
+}
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 12/33] target-tilegx: Generate SEGV properly
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (10 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 11/33] target-tilegx: Framework for decoding bundles Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-29 14:51 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 14/33] target-tilegx: Handle simple logical operations Richard Henderson
` (20 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
linux-user/main.c | 3 +++
target-tilegx/cpu.c | 5 ++++-
target-tilegx/cpu.h | 2 ++
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index 2d4b0b4..5ca09d2 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3685,6 +3685,9 @@ void cpu_loop(CPUTLGState *env)
case TILEGX_EXCP_REG_UDN_ACCESS:
gen_sigill_reg(env);
break;
+ case TILEGX_EXCP_SEGV:
+ gen_sigsegv_mapper(env, env->excaddr);
+ break;
default:
fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
g_assert_not_reached();
diff --git a/target-tilegx/cpu.c b/target-tilegx/cpu.c
index 87aee24..78b73e4 100644
--- a/target-tilegx/cpu.c
+++ b/target-tilegx/cpu.c
@@ -119,7 +119,10 @@ static void tilegx_cpu_do_interrupt(CPUState *cs)
static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
- cpu_dump_state(cs, stderr, fprintf, 0);
+ TileGXCPU *cpu = TILEGX_CPU(cs);
+
+ cs->exception_index = TILEGX_EXCP_SEGV;
+ cpu->env.excaddr = address;
return 1;
}
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
index 2c86cd3..3a62d20 100644
--- a/target-tilegx/cpu.h
+++ b/target-tilegx/cpu.h
@@ -60,6 +60,7 @@ enum {
typedef enum {
TILEGX_EXCP_NONE = 0,
TILEGX_EXCP_SYSCALL = 1,
+ TILEGX_EXCP_SEGV = 2,
TILEGX_EXCP_OPCODE_UNKNOWN = 0x101,
TILEGX_EXCP_OPCODE_UNIMPLEMENTED = 0x102,
TILEGX_EXCP_OPCODE_CMPEXCH = 0x103,
@@ -87,6 +88,7 @@ typedef struct CPUTLGState {
#if defined(CONFIG_USER_ONLY)
uint32_t excparam; /* exception parameter */
+ uint64_t excaddr; /* exception address */
#endif
CPU_COMMON
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 14/33] target-tilegx: Handle simple logical operations
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (11 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 12/33] target-tilegx: Generate SEGV properly Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-29 14:58 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 15/33] target-tilegx: Handle arithmetic instructions Richard Henderson
` (19 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 99 +++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 96 insertions(+), 3 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index a2d597d..066d351 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -106,9 +106,64 @@ static void gen_exception(DisasContext *dc, TileExcp num)
dc->exit_tb = true;
}
+static bool check_gr(DisasContext *dc, uint8_t reg)
+{
+ if (likely(reg < TILEGX_R_COUNT)) {
+ return true;
+ }
+
+ switch (reg) {
+ case TILEGX_R_SN:
+ case TILEGX_R_ZERO:
+ break;
+ case TILEGX_R_IDN0:
+ case TILEGX_R_IDN1:
+ gen_exception(dc, TILEGX_EXCP_REG_IDN_ACCESS);
+ break;
+ case TILEGX_R_UDN0:
+ case TILEGX_R_UDN1:
+ case TILEGX_R_UDN2:
+ case TILEGX_R_UDN3:
+ gen_exception(dc, TILEGX_EXCP_REG_UDN_ACCESS);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return false;
+}
+
+static TCGv load_zero(DisasContext *dc)
+{
+ if (TCGV_IS_UNUSED_I64(dc->zero)) {
+ dc->zero = tcg_const_i64(0);
+ }
+ return dc->zero;
+}
+
+static TCGv load_gr(DisasContext *dc, unsigned reg)
+{
+ if (check_gr(dc, reg)) {
+ return cpu_regs[reg];
+ }
+ return load_zero(dc);
+}
+
+static TCGv dest_gr(DisasContext *dc, unsigned reg)
+{
+ int n;
+
+ /* Skip the result, mark the exception if necessary, and continue */
+ check_gr(dc, reg);
+
+ n = dc->num_wb++;
+ dc->wb[n].reg = reg;
+ return dc->wb[n].val = tcg_temp_new_i64();
+}
+
static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca)
{
+ TCGv tdest, tsrca;
const char *mnemonic;
/* Eliminate nops before doing anything else. */
@@ -132,6 +187,9 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
return TILEGX_EXCP_NONE;
}
+ tdest = dest_gr(dc, dest);
+ tsrca = load_gr(dc, srca);
+
switch (opext) {
case OE_RR_X0(CNTLZ):
case OE_RR_Y0(CNTLZ):
@@ -180,8 +238,12 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
case OE_RR_Y0(PCNT):
case OE_RR_X0(REVBITS):
case OE_RR_Y0(REVBITS):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RR_X0(REVBYTES):
case OE_RR_Y0(REVBYTES):
+ tcg_gen_bswap64_tl(tdest, tsrca);
+ mnemonic = "revbytes";
+ break;
case OE_RR_X1(SWINT0):
case OE_RR_X1(SWINT1):
case OE_RR_X1(SWINT2):
@@ -207,6 +269,9 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca, unsigned srcb)
{
+ TCGv tdest = dest_gr(dc, dest);
+ TCGv tsrca = load_gr(dc, srca);
+ TCGv tsrcb = load_gr(dc, srcb);
const char *mnemonic;
switch (opext) {
@@ -220,10 +285,14 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(ADD, 0, X1):
case OE_RRR(ADD, 0, Y0):
case OE_RRR(ADD, 0, Y1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(AND, 0, X0):
case OE_RRR(AND, 0, X1):
case OE_RRR(AND, 5, Y0):
case OE_RRR(AND, 5, Y1):
+ tcg_gen_and_tl(tdest, tsrca, tsrcb);
+ mnemonic = "and";
+ break;
case OE_RRR(CMOVEQZ, 0, X0):
case OE_RRR(CMOVEQZ, 4, Y0):
case OE_RRR(CMOVNEZ, 0, X0):
@@ -334,14 +403,21 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(MZ, 0, X1):
case OE_RRR(MZ, 4, Y0):
case OE_RRR(MZ, 4, Y1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(NOR, 0, X0):
case OE_RRR(NOR, 0, X1):
case OE_RRR(NOR, 5, Y0):
case OE_RRR(NOR, 5, Y1):
+ tcg_gen_nor_tl(tdest, tsrca, tsrcb);
+ mnemonic = "nor";
+ break;
case OE_RRR(OR, 0, X0):
case OE_RRR(OR, 0, X1):
case OE_RRR(OR, 5, Y0):
case OE_RRR(OR, 5, Y1):
+ tcg_gen_or_tl(tdest, tsrca, tsrcb);
+ mnemonic = "or";
+ break;
case OE_RRR(ROTL, 0, X0):
case OE_RRR(ROTL, 0, X1):
case OE_RRR(ROTL, 6, Y0):
@@ -539,10 +615,14 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(V4SUBSC, 0, X1):
case OE_RRR(V4SUB, 0, X0):
case OE_RRR(V4SUB, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(XOR, 0, X0):
case OE_RRR(XOR, 0, X1):
case OE_RRR(XOR, 5, Y0):
case OE_RRR(XOR, 5, Y1):
+ tcg_gen_xor_tl(tdest, tsrca, tsrcb);
+ mnemonic = "xor";
+ break;
default:
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
}
@@ -555,6 +635,8 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca, int imm)
{
+ TCGv tdest = dest_gr(dc, dest);
+ TCGv tsrca = load_gr(dc, srca);
const char *mnemonic;
switch (opext) {
@@ -562,8 +644,14 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
case OE_IM(ADDI, X1):
case OE_IM(ADDXI, X0):
case OE_IM(ADDXI, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ case OE(ANDI_OPCODE_Y0, 0, Y0):
+ case OE(ANDI_OPCODE_Y1, 0, Y1):
case OE_IM(ANDI, X0):
case OE_IM(ANDI, X1):
+ tcg_gen_andi_tl(tdest, tsrca, imm);
+ mnemonic = "andi";
+ break;
case OE_IM(CMPEQI, X0):
case OE_IM(CMPEQI, X1):
case OE_IM(CMPLTSI, X0):
@@ -587,8 +675,12 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
case OE_IM(LWNA_ADD, X1):
case OE_IM(MFSPR, X1):
case OE_IM(MTSPR, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_IM(ORI, X0):
case OE_IM(ORI, X1):
+ tcg_gen_ori_tl(tdest, tsrca, imm);
+ mnemonic = "ori";
+ break;
case OE_IM(ST1_ADD, X1):
case OE_IM(ST2_ADD, X1):
case OE_IM(ST4_ADD, X1):
@@ -621,8 +713,12 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
case OE_IM(V2MAXSI, X1):
case OE_IM(V2MINSI, X0):
case OE_IM(V2MINSI, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_IM(XORI, X0):
case OE_IM(XORI, X1):
+ tcg_gen_xori_tl(tdest, tsrca, imm);
+ mnemonic = "xori";
+ break;
case OE_SH(ROTLI, X0):
case OE_SH(ROTLI, X1):
@@ -665,8 +761,6 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
case OE(ADDXI_OPCODE_Y1, 0, Y1):
case OE(ADDXLI_OPCODE_X0, 0, X0):
case OE(ADDXLI_OPCODE_X1, 0, X1):
- case OE(ANDI_OPCODE_Y0, 0, Y0):
- case OE(ANDI_OPCODE_Y1, 0, Y1):
case OE(CMPEQI_OPCODE_Y0, 0, Y0):
case OE(CMPEQI_OPCODE_Y1, 0, Y1):
case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
@@ -1057,7 +1151,6 @@ static inline void gen_intermediate_code_internal(TileGXCPU *cpu,
dc->jmp.cond = TCG_COND_NEVER;
TCGV_UNUSED_I64(dc->jmp.dest);
TCGV_UNUSED_I64(dc->jmp.val1);
- TCGV_UNUSED_I64(dc->jmp.val2);
TCGV_UNUSED_I64(dc->zero);
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 15/33] target-tilegx: Handle arithmetic instructions
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (12 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 14/33] target-tilegx: Handle simple logical operations Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-29 15:03 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 16/33] target-tilegx: Handle most bit manipulation instructions Richard Henderson
` (18 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 95 ++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 89 insertions(+), 6 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 066d351..090c006 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -160,6 +160,23 @@ static TCGv dest_gr(DisasContext *dc, unsigned reg)
return dc->wb[n].val = tcg_temp_new_i64();
}
+static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
+ void (*operate)(TCGv, TCGv, TCGv))
+{
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_ext32s_tl(tdest, tsrca);
+ tcg_gen_ext32s_tl(t0, tsrcb);
+ operate(tdest, tdest, t0);
+
+ tcg_gen_movi_tl(t0, 0x7fffffff);
+ tcg_gen_movcond_tl(TCG_COND_GT, tdest, tdest, t0, t0, tdest);
+ tcg_gen_movi_tl(t0, -0x80000000LL);
+ tcg_gen_movcond_tl(TCG_COND_LT, tdest, tdest, t0, t0, tdest);
+
+ tcg_temp_free(t0);
+}
+
static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca)
{
@@ -277,15 +294,24 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
switch (opext) {
case OE_RRR(ADDXSC, 0, X0):
case OE_RRR(ADDXSC, 0, X1):
+ gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_add_tl);
+ mnemonic = "addxsc";
+ break;
case OE_RRR(ADDX, 0, X0):
case OE_RRR(ADDX, 0, X1):
case OE_RRR(ADDX, 0, Y0):
case OE_RRR(ADDX, 0, Y1):
+ tcg_gen_add_tl(tdest, tsrca, tsrcb);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "addx";
+ break;
case OE_RRR(ADD, 0, X0):
case OE_RRR(ADD, 0, X1):
case OE_RRR(ADD, 0, Y0):
case OE_RRR(ADD, 0, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ tcg_gen_add_tl(tdest, tsrca, tsrcb);
+ mnemonic = "add";
+ break;
case OE_RRR(AND, 0, X0):
case OE_RRR(AND, 0, X1):
case OE_RRR(AND, 5, Y0):
@@ -422,30 +448,58 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(ROTL, 0, X1):
case OE_RRR(ROTL, 6, Y0):
case OE_RRR(ROTL, 6, Y1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(SHL1ADDX, 0, X0):
case OE_RRR(SHL1ADDX, 0, X1):
case OE_RRR(SHL1ADDX, 7, Y0):
case OE_RRR(SHL1ADDX, 7, Y1):
+ tcg_gen_shli_tl(tdest, tsrca, 1);
+ tcg_gen_add_tl(tdest, tdest, tsrcb);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "shl1addx";
+ break;
case OE_RRR(SHL1ADD, 0, X0):
case OE_RRR(SHL1ADD, 0, X1):
case OE_RRR(SHL1ADD, 1, Y0):
case OE_RRR(SHL1ADD, 1, Y1):
+ tcg_gen_shli_tl(tdest, tsrca, 1);
+ tcg_gen_add_tl(tdest, tdest, tsrcb);
+ mnemonic = "shl1add";
+ break;
case OE_RRR(SHL2ADDX, 0, X0):
case OE_RRR(SHL2ADDX, 0, X1):
case OE_RRR(SHL2ADDX, 7, Y0):
case OE_RRR(SHL2ADDX, 7, Y1):
+ tcg_gen_shli_tl(tdest, tsrca, 2);
+ tcg_gen_add_tl(tdest, tdest, tsrcb);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "shl2addx";
+ break;
case OE_RRR(SHL2ADD, 0, X0):
case OE_RRR(SHL2ADD, 0, X1):
case OE_RRR(SHL2ADD, 1, Y0):
case OE_RRR(SHL2ADD, 1, Y1):
+ tcg_gen_shli_tl(tdest, tsrca, 2);
+ tcg_gen_add_tl(tdest, tdest, tsrcb);
+ mnemonic = "shl2add";
+ break;
case OE_RRR(SHL3ADDX, 0, X0):
case OE_RRR(SHL3ADDX, 0, X1):
case OE_RRR(SHL3ADDX, 7, Y0):
case OE_RRR(SHL3ADDX, 7, Y1):
+ tcg_gen_shli_tl(tdest, tsrca, 3);
+ tcg_gen_add_tl(tdest, tdest, tsrcb);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "shl3addx";
+ break;
case OE_RRR(SHL3ADD, 0, X0):
case OE_RRR(SHL3ADD, 0, X1):
case OE_RRR(SHL3ADD, 1, Y0):
case OE_RRR(SHL3ADD, 1, Y1):
+ tcg_gen_shli_tl(tdest, tsrca, 3);
+ tcg_gen_add_tl(tdest, tdest, tsrcb);
+ mnemonic = "shl3add";
+ break;
case OE_RRR(SHLX, 0, X0):
case OE_RRR(SHLX, 0, X1):
case OE_RRR(SHL, 0, X0):
@@ -471,16 +525,27 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(STNT4, 0, X1):
case OE_RRR(STNT, 0, X1):
case OE_RRR(ST, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(SUBXSC, 0, X0):
case OE_RRR(SUBXSC, 0, X1):
+ gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_sub_tl);
+ mnemonic = "subxsc";
+ break;
case OE_RRR(SUBX, 0, X0):
case OE_RRR(SUBX, 0, X1):
case OE_RRR(SUBX, 0, Y0):
case OE_RRR(SUBX, 0, Y1):
+ tcg_gen_sub_tl(tdest, tsrca, tsrcb);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "subx";
+ break;
case OE_RRR(SUB, 0, X0):
case OE_RRR(SUB, 0, X1):
case OE_RRR(SUB, 0, Y0):
case OE_RRR(SUB, 0, Y1):
+ tcg_gen_sub_tl(tdest, tsrca, tsrcb);
+ mnemonic = "sub";
+ break;
case OE_RRR(V1ADDUC, 0, X0):
case OE_RRR(V1ADDUC, 0, X1):
case OE_RRR(V1ADD, 0, X0):
@@ -640,11 +705,21 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
const char *mnemonic;
switch (opext) {
+ case OE(ADDI_OPCODE_Y0, 0, Y0):
+ case OE(ADDI_OPCODE_Y1, 0, Y1):
case OE_IM(ADDI, X0):
case OE_IM(ADDI, X1):
+ tcg_gen_addi_tl(tdest, tsrca, imm);
+ mnemonic = "addi";
+ break;
+ case OE(ADDXI_OPCODE_Y0, 0, Y0):
+ case OE(ADDXI_OPCODE_Y1, 0, Y1):
case OE_IM(ADDXI, X0):
case OE_IM(ADDXI, X1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ tcg_gen_addi_tl(tdest, tsrca, imm);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "addxi";
+ break;
case OE(ANDI_OPCODE_Y0, 0, Y0):
case OE(ANDI_OPCODE_Y1, 0, Y1):
case OE_IM(ANDI, X0):
@@ -753,20 +828,28 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
case OE_SH(V2SHRUI, X0):
case OE_SH(V2SHRUI, X1):
- case OE(ADDI_OPCODE_Y0, 0, Y0):
- case OE(ADDI_OPCODE_Y1, 0, Y1):
case OE(ADDLI_OPCODE_X0, 0, X0):
case OE(ADDLI_OPCODE_X1, 0, X1):
- case OE(ADDXI_OPCODE_Y0, 0, Y0):
- case OE(ADDXI_OPCODE_Y1, 0, Y1):
+ tcg_gen_addi_tl(tdest, tsrca, imm);
+ mnemonic = "addli";
+ break;
case OE(ADDXLI_OPCODE_X0, 0, X0):
case OE(ADDXLI_OPCODE_X1, 0, X1):
+ tcg_gen_addi_tl(tdest, tsrca, imm);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "addxli";
+ break;
case OE(CMPEQI_OPCODE_Y0, 0, Y0):
case OE(CMPEQI_OPCODE_Y1, 0, Y1):
case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
case OE(CMPLTSI_OPCODE_Y1, 0, Y1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE(SHL16INSLI_OPCODE_X0, 0, X0):
case OE(SHL16INSLI_OPCODE_X1, 0, X1):
+ tcg_gen_shli_tl(tdest, tsrca, 16);
+ tcg_gen_ori_tl(tdest, tdest, imm & 0xffff);
+ mnemonic = "shl16insli";
+ break;
default:
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 16/33] target-tilegx: Handle most bit manipulation instructions
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (13 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 15/33] target-tilegx: Handle arithmetic instructions Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-29 15:26 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 17/33] target-tilegx: Handle basic load and store instructions Richard Henderson
` (17 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Omitting crc instructions.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/helper.c | 23 ++++++++++++++++++
target-tilegx/helper.h | 2 ++
target-tilegx/translate.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 84 insertions(+), 1 deletion(-)
diff --git a/target-tilegx/helper.c b/target-tilegx/helper.c
index ea66da0..6aba681 100644
--- a/target-tilegx/helper.c
+++ b/target-tilegx/helper.c
@@ -40,6 +40,29 @@ uint64_t helper_cnttz(uint64_t arg)
return ctz64(arg);
}
+uint64_t helper_pcnt(uint64_t arg)
+{
+ return ctpop64(arg);
+}
+
+uint64_t helper_revbits(uint64_t arg)
+{
+ /* Assign the correct byte position. */
+ arg = bswap64(arg);
+
+ /* Assign the correct nibble position. */
+ arg = ((arg & 0xf0f0f0f0f0f0f0f0ULL) >> 4)
+ | ((arg & 0x0f0f0f0f0f0f0f0fULL) << 4);
+
+ /* Assign the correct bit position. */
+ arg = ((arg & 0x8888888888888888ULL) >> 3)
+ | ((arg & 0x4444444444444444ULL) >> 1)
+ | ((arg & 0x2222222222222222ULL) << 1)
+ | ((arg & 0x1111111111111111ULL) << 3);
+
+ return arg;
+}
+
/*
* Functional Description
* uint64_t a = rf[SrcA];
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index fd5517e..644d313 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -1,4 +1,6 @@
DEF_HELPER_2(exception, noreturn, env, i32)
DEF_HELPER_FLAGS_1(cntlz, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_1(revbits, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 090c006..82a34e5 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -177,6 +177,35 @@ static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
tcg_temp_free(t0);
}
+static void gen_dblaligni(TCGv tdest, TCGv tsrca, TCGv tsrcb, int shr)
+{
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_shri_tl(t0, tsrcb, shr);
+ tcg_gen_shli_tl(tdest, tsrca, 64 - shr);
+ tcg_gen_or_tl(tdest, tdest, t0);
+
+ tcg_temp_free(t0);
+}
+
+static void gen_dblalign(TCGv tdest, TCGv tsrcd, TCGv tsrca, TCGv tsrcb)
+{
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_andi_tl(t0, tsrcb, 7);
+ tcg_gen_shli_tl(t0, t0, 3);
+ tcg_gen_shr_tl(tdest, tsrcd, t0);
+
+ /* Rather than creating and invalid shift, 64 - 0, perform the
+ left shift in two steps via the one's compliment. */
+ tcg_gen_xori_tl(t0, t0, 63);
+ tcg_gen_shl_tl(t0, tsrca, t0);
+ tcg_gen_shli_tl(t0, t0, 1);
+ tcg_gen_or_tl(tdest, tdest, t0);
+
+ tcg_temp_free(t0);
+}
+
static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca)
{
@@ -210,8 +239,14 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
switch (opext) {
case OE_RR_X0(CNTLZ):
case OE_RR_Y0(CNTLZ):
+ gen_helper_cntlz(tdest, tsrca);
+ mnemonic = "cntlz";
+ break;
case OE_RR_X0(CNTTZ):
case OE_RR_Y0(CNTTZ):
+ gen_helper_cnttz(tdest, tsrca);
+ mnemonic = "cnttz";
+ break;
case OE_RR_X1(DRAIN):
case OE_RR_X1(DTLBPR):
case OE_RR_X1(FINV):
@@ -251,11 +286,17 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
case OE_RR_Y1(LNK):
case OE_RR_X1(MF):
case OE_RR_X1(NAP):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RR_X0(PCNT):
case OE_RR_Y0(PCNT):
+ gen_helper_pcnt(tdest, tsrca);
+ mnemonic = "pcnt";
+ break;
case OE_RR_X0(REVBITS):
case OE_RR_Y0(REVBITS):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ gen_helper_revbits(tdest, tsrca);
+ mnemonic = "revbits";
+ break;
case OE_RR_X0(REVBYTES):
case OE_RR_Y0(REVBYTES):
tcg_gen_bswap64_tl(tdest, tsrca);
@@ -358,13 +399,26 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(CMUL, 0, X0):
case OE_RRR(CRC32_32, 0, X0):
case OE_RRR(CRC32_8, 0, X0):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(DBLALIGN2, 0, X0):
case OE_RRR(DBLALIGN2, 0, X1):
+ gen_dblaligni(tdest, tsrca, tsrcb, 16);
+ mnemonic = "dblalign2";
+ break;
case OE_RRR(DBLALIGN4, 0, X0):
case OE_RRR(DBLALIGN4, 0, X1):
+ gen_dblaligni(tdest, tsrca, tsrcb, 32);
+ mnemonic = "dblalign4";
+ break;
case OE_RRR(DBLALIGN6, 0, X0):
case OE_RRR(DBLALIGN6, 0, X1):
+ gen_dblaligni(tdest, tsrca, tsrcb, 48);
+ mnemonic = "dblalign6";
+ break;
case OE_RRR(DBLALIGN, 0, X0):
+ gen_dblalign(tdest, load_gr(dc, dest), tsrca, tsrcb);
+ mnemonic = "dblalign";
+ break;
case OE_RRR(EXCH4, 0, X1):
case OE_RRR(EXCH, 0, X1):
case OE_RRR(FDOUBLE_ADDSUB, 0, X0):
@@ -516,7 +570,11 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(SHRU, 0, X1):
case OE_RRR(SHRU, 6, Y0):
case OE_RRR(SHRU, 6, Y1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(SHUFFLEBYTES, 0, X0):
+ gen_helper_shufflebytes(tdest, load_gr(dc, dest), tsrca, tsrca);
+ mnemonic = "shufflebytes";
+ break;
case OE_RRR(ST1, 0, X1):
case OE_RRR(ST2, 0, X1):
case OE_RRR(ST4, 0, X1):
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 17/33] target-tilegx: Handle basic load and store instructions
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (14 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 16/33] target-tilegx: Handle most bit manipulation instructions Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-29 20:45 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 18/33] target-tilegx: Handle post-increment " Richard Henderson
` (16 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 131 ++++++++++++++++++++++++++++++++++++++++------
1 file changed, 116 insertions(+), 15 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 82a34e5..ddee2b0 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -206,11 +206,27 @@ static void gen_dblalign(TCGv tdest, TCGv tsrcd, TCGv tsrca, TCGv tsrcb)
tcg_temp_free(t0);
}
+static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,
+ unsigned srcb, TCGMemOp memop, const char *name)
+{
+ if (dest) {
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ }
+
+ tcg_gen_qemu_st_tl(load_gr(dc, srcb), load_gr(dc, srca),
+ dc->mmuidx, memop);
+
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", name,
+ reg_names[srca], reg_names[srcb]);
+ return TILEGX_EXCP_NONE;
+}
+
static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca)
{
TCGv tdest, tsrca;
const char *mnemonic;
+ TCGMemOp memop;
/* Eliminate nops before doing anything else. */
switch (opext) {
@@ -267,21 +283,70 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
case OE_RR_Y1(JRP):
case OE_RR_X1(JR):
case OE_RR_Y1(JR):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RR_X1(LD1S):
+ memop = MO_SB;
+ mnemonic = "ld1s";
+ goto do_load;
case OE_RR_X1(LD1U):
+ memop = MO_UB;
+ mnemonic = "ld1u";
+ goto do_load;
case OE_RR_X1(LD2S):
+ memop = MO_TESW;
+ mnemonic = "ld2s";
+ goto do_load;
case OE_RR_X1(LD2U):
+ memop = MO_TEUW;
+ mnemonic = "ld2u";
+ goto do_load;
case OE_RR_X1(LD4S):
+ memop = MO_TESL;
+ mnemonic = "ld4s";
+ goto do_load;
case OE_RR_X1(LD4U):
- case OE_RR_X1(LDNA):
+ memop = MO_TEUL;
+ mnemonic = "ld4u";
+ goto do_load;
case OE_RR_X1(LDNT1S):
+ memop = MO_SB;
+ mnemonic = "ldnt1s";
+ goto do_load;
case OE_RR_X1(LDNT1U):
+ memop = MO_UB;
+ mnemonic = "ldnt1u";
+ goto do_load;
case OE_RR_X1(LDNT2S):
+ memop = MO_TESW;
+ mnemonic = "ldnt2s";
+ goto do_load;
case OE_RR_X1(LDNT2U):
+ memop = MO_TEUW;
+ mnemonic = "ldnt2u";
+ goto do_load;
case OE_RR_X1(LDNT4S):
+ memop = MO_TESL;
+ mnemonic = "ldnt4s";
+ goto do_load;
case OE_RR_X1(LDNT4U):
+ memop = MO_TEUL;
+ mnemonic = "ldnt4u";
+ goto do_load;
case OE_RR_X1(LDNT):
+ memop = MO_TEQ;
+ mnemonic = "ldnt";
+ goto do_load;
case OE_RR_X1(LD):
+ memop = MO_TEQ;
+ mnemonic = "ld";
+ do_load:
+ tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
+ break;
+ case OE_RR_X1(LDNA):
+ tcg_gen_andi_tl(tdest, tsrca, ~7);
+ tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ);
+ mnemonic = "ldna";
+ break;
case OE_RR_X1(LNK):
case OE_RR_Y1(LNK):
case OE_RR_X1(MF):
@@ -575,15 +640,6 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
gen_helper_shufflebytes(tdest, load_gr(dc, dest), tsrca, tsrca);
mnemonic = "shufflebytes";
break;
- case OE_RRR(ST1, 0, X1):
- case OE_RRR(ST2, 0, X1):
- case OE_RRR(ST4, 0, X1):
- case OE_RRR(STNT1, 0, X1):
- case OE_RRR(STNT2, 0, X1):
- case OE_RRR(STNT4, 0, X1):
- case OE_RRR(STNT, 0, X1):
- case OE_RRR(ST, 0, X1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(SUBXSC, 0, X0):
case OE_RRR(SUBXSC, 0, X1):
gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_sub_tl);
@@ -1089,27 +1145,55 @@ static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
unsigned srca = get_SrcA_Y2(bundle);
unsigned srcbdest = get_SrcBDest_Y2(bundle);
const char *mnemonic;
+ TCGMemOp memop;
switch (OEY2(opc, mode)) {
case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2):
+ memop = MO_SB;
+ mnemonic = "ld1s";
+ goto do_load;
case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2):
+ memop = MO_UB;
+ mnemonic = "ld1u";
+ goto do_load;
case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2):
+ memop = MO_TESW;
+ mnemonic = "ld2s";
+ goto do_load;
case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2):
+ memop = MO_TEUW;
+ mnemonic = "ld2u";
+ goto do_load;
case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2):
+ memop = MO_TESL;
+ mnemonic = "ld4s";
+ goto do_load;
case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2):
+ memop = MO_TEUL;
+ mnemonic = "ld4u";
+ goto do_load;
case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2):
+ memop = MO_TEQ;
+ mnemonic = "ld";
+ do_load:
+ tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
+ dc->mmuidx, memop);
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
+ reg_names[srcbdest], reg_names[srca]);
+ return TILEGX_EXCP_NONE;
case OEY2(ST1_OPCODE_Y2, MODE_OPCODE_YC2):
+ return gen_st_opcode(dc, 0, srca, srcbdest, MO_UB, "st1");
case OEY2(ST2_OPCODE_Y2, MODE_OPCODE_YC2):
+ return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUW, "st2");
case OEY2(ST4_OPCODE_Y2, MODE_OPCODE_YC2):
+ return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUL, "st4");
case OEY2(ST_OPCODE_Y2, MODE_OPCODE_YC2):
+ return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEQ, "st");
default:
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
}
- qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
- reg_names[srca], reg_names[srcbdest]);
- return TILEGX_EXCP_NONE;
}
static TileExcp decode_x0(DisasContext *dc, tilegx_bundle_bits bundle)
@@ -1168,11 +1252,28 @@ static TileExcp decode_x1(DisasContext *dc, tilegx_bundle_bits bundle)
switch (opc) {
case RRR_0_OPCODE_X1:
ext = get_RRROpcodeExtension_X1(bundle);
- if (ext == UNARY_RRR_0_OPCODE_X1) {
+ srcb = get_SrcB_X1(bundle);
+ switch (ext) {
+ case UNARY_RRR_0_OPCODE_X1:
ext = get_UnaryOpcodeExtension_X1(bundle);
return gen_rr_opcode(dc, OE(opc, ext, X1), dest, srca);
+ case ST1_RRR_0_OPCODE_X1:
+ return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "st1");
+ case ST2_RRR_0_OPCODE_X1:
+ return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "st2");
+ case ST4_RRR_0_OPCODE_X1:
+ return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "st4");
+ case STNT1_RRR_0_OPCODE_X1:
+ return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "stnt1");
+ case STNT2_RRR_0_OPCODE_X1:
+ return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "stnt2");
+ case STNT4_RRR_0_OPCODE_X1:
+ return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "stnt4");
+ case STNT_RRR_0_OPCODE_X1:
+ return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "stnt");
+ case ST_RRR_0_OPCODE_X1:
+ return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "st");
}
- srcb = get_SrcB_X1(bundle);
return gen_rrr_opcode(dc, OE(opc, ext, X1), dest, srca, srcb);
case SHIFT_OPCODE_X1:
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 18/33] target-tilegx: Handle post-increment load and store instructions
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (15 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 17/33] target-tilegx: Handle basic load and store instructions Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-29 20:52 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 19/33] target-tilegx: Handle unconditional jump instructions Richard Henderson
` (15 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 96 ++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 87 insertions(+), 9 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index ddee2b0..37c6ec5 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -221,6 +221,20 @@ static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,
return TILEGX_EXCP_NONE;
}
+static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigned srcb,
+ int imm, TCGMemOp memop, const char *name)
+{
+ TCGv tsrca = load_gr(dc, srca);
+ TCGv tsrcb = load_gr(dc, srcb);
+
+ tcg_gen_qemu_st_tl(tsrcb, tsrca, dc->mmuidx, memop);
+ tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
+
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", name,
+ reg_names[srca], reg_names[srcb], imm);
+ return TILEGX_EXCP_NONE;
+}
+
static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
unsigned dest, unsigned srca)
{
@@ -817,6 +831,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
TCGv tdest = dest_gr(dc, dest);
TCGv tsrca = load_gr(dc, srca);
const char *mnemonic;
+ TCGMemOp memop;
switch (opext) {
case OE(ADDI_OPCODE_Y0, 0, Y0):
@@ -847,21 +862,72 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
case OE_IM(CMPLTSI, X1):
case OE_IM(CMPLTUI, X0):
case OE_IM(CMPLTUI, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_IM(LD1S_ADD, X1):
+ memop = MO_SB;
+ mnemonic = "ld1s_add";
+ goto do_load_add;
case OE_IM(LD1U_ADD, X1):
+ memop = MO_UB;
+ mnemonic = "ld1u_add";
+ goto do_load_add;
case OE_IM(LD2S_ADD, X1):
+ memop = MO_TESW;
+ mnemonic = "ld2s_add";
+ goto do_load_add;
case OE_IM(LD2U_ADD, X1):
+ memop = MO_TEUW;
+ mnemonic = "ld2u_add";
+ goto do_load_add;
case OE_IM(LD4S_ADD, X1):
+ memop = MO_TESL;
+ mnemonic = "ld4s_add";
+ goto do_load_add;
case OE_IM(LD4U_ADD, X1):
+ memop = MO_TEUL;
+ mnemonic = "ld4u_add";
+ goto do_load_add;
case OE_IM(LDNT1S_ADD, X1):
+ memop = MO_SB;
+ mnemonic = "ldnt1s_add";
+ goto do_load_add;
case OE_IM(LDNT1U_ADD, X1):
+ memop = MO_UB;
+ mnemonic = "ldnt1u_add";
+ goto do_load_add;
case OE_IM(LDNT2S_ADD, X1):
+ memop = MO_TESW;
+ mnemonic = "ldnt2s_add";
+ goto do_load_add;
case OE_IM(LDNT2U_ADD, X1):
+ memop = MO_TEUW;
+ mnemonic = "ldnt2u_add";
+ goto do_load_add;
case OE_IM(LDNT4S_ADD, X1):
+ memop = MO_TESL;
+ mnemonic = "ldnt4s_add";
+ goto do_load_add;
case OE_IM(LDNT4U_ADD, X1):
+ memop = MO_TEUL;
+ mnemonic = "ldnt4u_add";
+ goto do_load_add;
case OE_IM(LDNT_ADD, X1):
+ memop = MO_TEQ;
+ mnemonic = "ldnt_add";
+ goto do_load_add;
case OE_IM(LD_ADD, X1):
- case OE_IM(LWNA_ADD, X1):
+ memop = MO_TEQ;
+ mnemonic = "ldnt_add";
+ do_load_add:
+ tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
+ tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
+ break;
+ case OE_IM(LDNA_ADD, X1):
+ tcg_gen_andi_tl(tdest, tsrca, ~7);
+ tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ);
+ tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
+ mnemonic = "ldna_add";
+ break;
case OE_IM(MFSPR, X1):
case OE_IM(MTSPR, X1):
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
@@ -870,14 +936,6 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
tcg_gen_ori_tl(tdest, tsrca, imm);
mnemonic = "ori";
break;
- case OE_IM(ST1_ADD, X1):
- case OE_IM(ST2_ADD, X1):
- case OE_IM(ST4_ADD, X1):
- case OE_IM(STNT1_ADD, X1):
- case OE_IM(STNT2_ADD, X1):
- case OE_IM(STNT4_ADD, X1):
- case OE_IM(STNT_ADD, X1):
- case OE_IM(ST_ADD, X1):
case OE_IM(V1ADDI, X0):
case OE_IM(V1ADDI, X1):
case OE_IM(V1CMPEQI, X0):
@@ -1283,6 +1341,26 @@ static TileExcp decode_x1(DisasContext *dc, tilegx_bundle_bits bundle)
case IMM8_OPCODE_X1:
ext = get_Imm8OpcodeExtension_X1(bundle);
+ imm = (int8_t)get_Dest_Imm8_X1(bundle);
+ srcb = get_SrcB_X1(bundle);
+ switch (ext) {
+ case ST1_ADD_IMM8_OPCODE_X1:
+ return gen_st_add_opcode(dc, srca, srcb, imm, MO_UB, "st1_add");
+ case ST2_ADD_IMM8_OPCODE_X1:
+ return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUW, "st2_add");
+ case ST4_ADD_IMM8_OPCODE_X1:
+ return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUL, "st4_add");
+ case STNT1_ADD_IMM8_OPCODE_X1:
+ return gen_st_add_opcode(dc, srca, srcb, imm, MO_UB, "stnt1_add");
+ case STNT2_ADD_IMM8_OPCODE_X1:
+ return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUW, "stnt2_add");
+ case STNT4_ADD_IMM8_OPCODE_X1:
+ return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUL, "stnt4_add");
+ case STNT_ADD_IMM8_OPCODE_X1:
+ return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEQ, "stnt_add");
+ case ST_ADD_IMM8_OPCODE_X1:
+ return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEQ, "st_add");
+ }
imm = (int8_t)get_Imm8_X1(bundle);
return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 19/33] target-tilegx: Handle unconditional jump instructions
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (16 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 18/33] target-tilegx: Handle post-increment " Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-29 21:00 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 20/33] target-tilegx: Handle conditional branch instructions Richard Henderson
` (14 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 58 +++++++++++++++++++++++++++++++++--------------
1 file changed, 41 insertions(+), 17 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 37c6ec5..11dcd45 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -242,7 +242,7 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
const char *mnemonic;
TCGMemOp memop;
- /* Eliminate nops before doing anything else. */
+ /* Eliminate nops and jumps before doing anything else. */
switch (opext) {
case OE_RR_Y0(NOP):
case OE_RR_Y1(NOP):
@@ -261,6 +261,31 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
return TILEGX_EXCP_NONE;
+
+ case OE_RR_X1(JRP):
+ case OE_RR_Y1(JRP):
+ mnemonic = "jrp";
+ goto do_jr;
+ case OE_RR_X1(JR):
+ case OE_RR_Y1(JR):
+ mnemonic = "jr";
+ goto do_jr;
+ case OE_RR_X1(JALRP):
+ case OE_RR_Y1(JALRP):
+ mnemonic = "jalrp";
+ goto do_jalr;
+ case OE_RR_X1(JALR):
+ case OE_RR_Y1(JALR):
+ mnemonic = "jalr";
+ do_jalr:
+ tcg_gen_movi_tl(dest_gr(dc, TILEGX_R_LR),
+ dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
+ do_jr:
+ dc->jmp.cond = TCG_COND_ALWAYS;
+ dc->jmp.dest = tcg_temp_new();
+ tcg_gen_andi_tl(dc->jmp.dest, load_gr(dc, srca), ~7);
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);
+ return TILEGX_EXCP_NONE;
}
tdest = dest_gr(dc, dest);
@@ -289,14 +314,6 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
case OE_RR_Y1(ILL):
case OE_RR_X1(INV):
case OE_RR_X1(IRET):
- case OE_RR_X1(JALRP):
- case OE_RR_Y1(JALRP):
- case OE_RR_X1(JALR):
- case OE_RR_Y1(JALR):
- case OE_RR_X1(JRP):
- case OE_RR_Y1(JRP):
- case OE_RR_X1(JR):
- case OE_RR_Y1(JR):
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RR_X1(LD1S):
memop = MO_SB;
@@ -363,6 +380,12 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
break;
case OE_RR_X1(LNK):
case OE_RR_Y1(LNK):
+ if (srca) {
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ }
+ tcg_gen_movi_tl(tdest, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
+ mnemonic = "lnk";
+ break;
case OE_RR_X1(MF):
case OE_RR_X1(NAP):
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
@@ -1086,18 +1109,19 @@ static TileExcp gen_branch_opcode_x1(DisasContext *dc, unsigned ext,
return TILEGX_EXCP_NONE;
}
-static TileExcp gen_jump_opcode_x1(DisasContext *dc, unsigned ext,
- int off)
+static TileExcp gen_jump_opcode_x1(DisasContext *dc, unsigned ext, int off)
{
target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
- const char *mnemonic;
+ const char *mnemonic = "j";
- switch (ext) {
- case JAL_JUMP_OPCODE_X1:
- case J_JUMP_OPCODE_X1:
- default:
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ /* The extension field is 1 bit, therefore we only have JAL and J. */
+ if (ext == JAL_JUMP_OPCODE_X1) {
+ tcg_gen_movi_tl(dest_gr(dc, TILEGX_R_LR),
+ dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
+ mnemonic = "jal";
}
+ dc->jmp.cond = TCG_COND_ALWAYS;
+ dc->jmp.dest = tcg_const_tl(tgt);
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
qemu_log("%s " TARGET_FMT_lx " <%s>",
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 20/33] target-tilegx: Handle conditional branch instructions
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (17 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 19/33] target-tilegx: Handle unconditional jump instructions Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-29 21:08 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 21/33] target-tilegx: Handle comparison instructions Richard Henderson
` (13 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 51 +++++++++++++++++++++++++++++++++++------------
1 file changed, 38 insertions(+), 13 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 11dcd45..ddeb65f 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1081,30 +1081,55 @@ static TileExcp gen_branch_opcode_x1(DisasContext *dc, unsigned ext,
target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
const char *mnemonic;
- switch (ext) {
- case BEQZT_BRANCH_OPCODE_X1:
+ dc->jmp.dest = tcg_const_tl(tgt);
+ dc->jmp.val1 = tcg_temp_new();
+ tcg_gen_mov_tl(dc->jmp.val1, load_gr(dc, srca));
+
+ /* Note that the "predict taken" opcodes have bit 0 clear.
+ Therefore, fold the two cases together by setting bit 0. */
+ switch (ext | 1) {
case BEQZ_BRANCH_OPCODE_X1:
- case BNEZT_BRANCH_OPCODE_X1:
+ dc->jmp.cond = TCG_COND_EQ;
+ mnemonic = "beqz";
+ break;
case BNEZ_BRANCH_OPCODE_X1:
- case BLBC_BRANCH_OPCODE_X1:
- case BGEZT_BRANCH_OPCODE_X1:
+ dc->jmp.cond = TCG_COND_NE;
+ mnemonic = "bnez";
+ break;
case BGEZ_BRANCH_OPCODE_X1:
- case BGTZT_BRANCH_OPCODE_X1:
+ dc->jmp.cond = TCG_COND_GE;
+ mnemonic = "bgez";
+ break;
case BGTZ_BRANCH_OPCODE_X1:
- case BLBCT_BRANCH_OPCODE_X1:
- case BLBST_BRANCH_OPCODE_X1:
- case BLBS_BRANCH_OPCODE_X1:
- case BLEZT_BRANCH_OPCODE_X1:
+ dc->jmp.cond = TCG_COND_GT;
+ mnemonic = "bgtz";
+ break;
case BLEZ_BRANCH_OPCODE_X1:
- case BLTZT_BRANCH_OPCODE_X1:
+ dc->jmp.cond = TCG_COND_LE;
+ mnemonic = "blez";
+ break;
case BLTZ_BRANCH_OPCODE_X1:
+ dc->jmp.cond = TCG_COND_LT;
+ mnemonic = "bltz";
+ break;
+ case BLBC_BRANCH_OPCODE_X1:
+ dc->jmp.cond = TCG_COND_EQ;
+ tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1);
+ mnemonic = "blbc";
+ break;
+ case BLBS_BRANCH_OPCODE_X1:
+ dc->jmp.cond = TCG_COND_NE;
+ tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1);
+ mnemonic = "blbs";
+ break;
default:
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
}
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
- qemu_log("%s %s, " TARGET_FMT_lx " <%s>",
- mnemonic, reg_names[srca], tgt, lookup_symbol(tgt));
+ qemu_log("%s%s %s, " TARGET_FMT_lx " <%s>",
+ mnemonic, ext & 1 ? "" : "t",
+ reg_names[srca], tgt, lookup_symbol(tgt));
}
return TILEGX_EXCP_NONE;
}
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 21/33] target-tilegx: Handle comparison instructions
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (18 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 20/33] target-tilegx: Handle conditional branch instructions Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-29 21:12 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 22/33] target-tilegx: Implement system and memory management instructions Richard Henderson
` (12 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 39 +++++++++++++++++++++++++++++++++------
1 file changed, 33 insertions(+), 6 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index ddeb65f..ea68902 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -466,32 +466,52 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(CMOVEQZ, 4, Y0):
case OE_RRR(CMOVNEZ, 0, X0):
case OE_RRR(CMOVNEZ, 4, Y0):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(CMPEQ, 0, X0):
case OE_RRR(CMPEQ, 0, X1):
case OE_RRR(CMPEQ, 3, Y0):
case OE_RRR(CMPEQ, 3, Y1):
+ tcg_gen_setcond_tl(TCG_COND_EQ, tdest, tsrca, tsrcb);
+ mnemonic = "cmpeq";
+ break;
case OE_RRR(CMPEXCH4, 0, X1):
case OE_RRR(CMPEXCH, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(CMPLES, 0, X0):
case OE_RRR(CMPLES, 0, X1):
case OE_RRR(CMPLES, 2, Y0):
case OE_RRR(CMPLES, 2, Y1):
+ tcg_gen_setcond_tl(TCG_COND_LE, tdest, tsrca, tsrcb);
+ mnemonic = "cmples";
+ break;
case OE_RRR(CMPLEU, 0, X0):
case OE_RRR(CMPLEU, 0, X1):
case OE_RRR(CMPLEU, 2, Y0):
case OE_RRR(CMPLEU, 2, Y1):
+ tcg_gen_setcond_tl(TCG_COND_LEU, tdest, tsrca, tsrcb);
+ mnemonic = "cmpleu";
+ break;
case OE_RRR(CMPLTS, 0, X0):
case OE_RRR(CMPLTS, 0, X1):
case OE_RRR(CMPLTS, 2, Y0):
case OE_RRR(CMPLTS, 2, Y1):
+ tcg_gen_setcond_tl(TCG_COND_LT, tdest, tsrca, tsrcb);
+ mnemonic = "cmplts";
+ break;
case OE_RRR(CMPLTU, 0, X0):
case OE_RRR(CMPLTU, 0, X1):
case OE_RRR(CMPLTU, 2, Y0):
case OE_RRR(CMPLTU, 2, Y1):
+ tcg_gen_setcond_tl(TCG_COND_LTU, tdest, tsrca, tsrcb);
+ mnemonic = "cmpltu";
+ break;
case OE_RRR(CMPNE, 0, X0):
case OE_RRR(CMPNE, 0, X1):
case OE_RRR(CMPNE, 3, Y0):
case OE_RRR(CMPNE, 3, Y1):
+ tcg_gen_setcond_tl(TCG_COND_NE, tdest, tsrca, tsrcb);
+ mnemonic = "cmpne";
+ break;
case OE_RRR(CMULAF, 0, X0):
case OE_RRR(CMULA, 0, X0):
case OE_RRR(CMULFR, 0, X0):
@@ -879,13 +899,25 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
tcg_gen_andi_tl(tdest, tsrca, imm);
mnemonic = "andi";
break;
+ case OE(CMPEQI_OPCODE_Y0, 0, Y0):
+ case OE(CMPEQI_OPCODE_Y1, 0, Y1):
case OE_IM(CMPEQI, X0):
case OE_IM(CMPEQI, X1):
+ tcg_gen_setcondi_tl(TCG_COND_EQ, tdest, tsrca, imm);
+ mnemonic = "cmpeqi";
+ break;
+ case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
+ case OE(CMPLTSI_OPCODE_Y1, 0, Y1):
case OE_IM(CMPLTSI, X0):
case OE_IM(CMPLTSI, X1):
+ tcg_gen_setcondi_tl(TCG_COND_LT, tdest, tsrca, imm);
+ mnemonic = "cmpltsi";
+ break;
case OE_IM(CMPLTUI, X0):
case OE_IM(CMPLTUI, X1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ tcg_gen_setcondi_tl(TCG_COND_LTU, tdest, tsrca, imm);
+ mnemonic = "cmpltui";
+ break;
case OE_IM(LD1S_ADD, X1):
memop = MO_SB;
mnemonic = "ld1s_add";
@@ -1034,11 +1066,6 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
tcg_gen_ext32s_tl(tdest, tdest);
mnemonic = "addxli";
break;
- case OE(CMPEQI_OPCODE_Y0, 0, Y0):
- case OE(CMPEQI_OPCODE_Y1, 0, Y1):
- case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
- case OE(CMPLTSI_OPCODE_Y1, 0, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE(SHL16INSLI_OPCODE_X0, 0, X0):
case OE(SHL16INSLI_OPCODE_X1, 0, X1):
tcg_gen_shli_tl(tdest, tsrca, 16);
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 22/33] target-tilegx: Implement system and memory management instructions
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (19 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 21/33] target-tilegx: Handle comparison instructions Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-29 21:21 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 23/33] target-tilegx: Handle bitfield instructions Richard Henderson
` (11 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Most of which are either nops or exceptions.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 94 ++++++++++++++++++++++++++++++++++-------------
1 file changed, 68 insertions(+), 26 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index ea68902..5bdc8be 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -241,27 +241,82 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
TCGv tdest, tsrca;
const char *mnemonic;
TCGMemOp memop;
+ TileExcp ret = TILEGX_EXCP_NONE;
- /* Eliminate nops and jumps before doing anything else. */
+ /* Eliminate instructions with no output before doing anything else. */
switch (opext) {
case OE_RR_Y0(NOP):
case OE_RR_Y1(NOP):
case OE_RR_X0(NOP):
case OE_RR_X1(NOP):
mnemonic = "nop";
- goto do_nop;
+ goto done0;
case OE_RR_Y0(FNOP):
case OE_RR_Y1(FNOP):
case OE_RR_X0(FNOP):
case OE_RR_X1(FNOP):
mnemonic = "fnop";
- do_nop:
- if (srca || dest) {
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ goto done0;
+ case OE_RR_X1(DRAIN):
+ mnemonic = "drain";
+ goto done0;
+ case OE_RR_X1(FLUSHWB):
+ mnemonic = "flushwb";
+ goto done0;
+ case OE_RR_X1(ILL):
+ case OE_RR_Y1(ILL):
+ ret = TILEGX_EXCP_OPCODE_UNKNOWN;
+ mnemonic = (dest == 0x1c && srca == 0x25 ? "bpt" : "ill");
+ goto done0;
+ case OE_RR_X1(MF):
+ mnemonic = "mf";
+ goto done0;
+ case OE_RR_X1(NAP):
+ /* ??? This should yield, especially in system mode. */
+ mnemonic = "nap";
+ goto done0;
+ case OE_RR_X1(SWINT0):
+ ret = TILEGX_EXCP_OPCODE_UNKNOWN;
+ mnemonic = "swint0";
+ goto done0;
+ case OE_RR_X1(SWINT1):
+ ret = TILEGX_EXCP_SYSCALL;
+ mnemonic = "swint1";
+ goto done0;
+ case OE_RR_X1(SWINT2):
+ ret = TILEGX_EXCP_OPCODE_UNKNOWN;
+ mnemonic = "swint2";
+ goto done0;
+ case OE_RR_X1(SWINT3):
+ ret = TILEGX_EXCP_OPCODE_UNKNOWN;
+ mnemonic = "swint3";
+ goto done0;
+ done0:
+ if ((srca || dest) && ret == TILEGX_EXCP_NONE) {
+ ret = TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
- return TILEGX_EXCP_NONE;
+ return ret;
+ case OE_RR_X1(DTLBPR):
+ ret = TILEGX_EXCP_OPCODE_UNKNOWN;
+ mnemonic = "dtlbpr";
+ goto done1;
+ case OE_RR_X1(FINV):
+ mnemonic = "finv";
+ goto done1;
+ case OE_RR_X1(FLUSH):
+ mnemonic = "flush";
+ goto done1;
+ case OE_RR_X1(ICOH):
+ mnemonic = "icoh";
+ goto done1;
+ case OE_RR_X1(INV):
+ mnemonic = "inv";
+ goto done1;
+ case OE_RR_X1(WH64):
+ mnemonic = "wh64";
+ goto done1;
case OE_RR_X1(JRP):
case OE_RR_Y1(JRP):
mnemonic = "jrp";
@@ -284,8 +339,12 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
dc->jmp.cond = TCG_COND_ALWAYS;
dc->jmp.dest = tcg_temp_new();
tcg_gen_andi_tl(dc->jmp.dest, load_gr(dc, srca), ~7);
+ done1:
+ if (dest && ret == TILEGX_EXCP_NONE) {
+ ret = TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ }
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);
- return TILEGX_EXCP_NONE;
+ return ret;
}
tdest = dest_gr(dc, dest);
@@ -302,17 +361,8 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
gen_helper_cnttz(tdest, tsrca);
mnemonic = "cnttz";
break;
- case OE_RR_X1(DRAIN):
- case OE_RR_X1(DTLBPR):
- case OE_RR_X1(FINV):
- case OE_RR_X1(FLUSHWB):
- case OE_RR_X1(FLUSH):
case OE_RR_X0(FSINGLE_PACK1):
case OE_RR_Y0(FSINGLE_PACK1):
- case OE_RR_X1(ICOH):
- case OE_RR_X1(ILL):
- case OE_RR_Y1(ILL):
- case OE_RR_X1(INV):
case OE_RR_X1(IRET):
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RR_X1(LD1S):
@@ -381,14 +431,11 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
case OE_RR_X1(LNK):
case OE_RR_Y1(LNK):
if (srca) {
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ ret = TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
}
tcg_gen_movi_tl(tdest, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
mnemonic = "lnk";
break;
- case OE_RR_X1(MF):
- case OE_RR_X1(NAP):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RR_X0(PCNT):
case OE_RR_Y0(PCNT):
gen_helper_pcnt(tdest, tsrca);
@@ -404,10 +451,6 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
tcg_gen_bswap64_tl(tdest, tsrca);
mnemonic = "revbytes";
break;
- case OE_RR_X1(SWINT0):
- case OE_RR_X1(SWINT1):
- case OE_RR_X1(SWINT2):
- case OE_RR_X1(SWINT3):
case OE_RR_X0(TBLIDXB0):
case OE_RR_Y0(TBLIDXB0):
case OE_RR_X0(TBLIDXB1):
@@ -416,14 +459,13 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
case OE_RR_Y0(TBLIDXB2):
case OE_RR_X0(TBLIDXB3):
case OE_RR_Y0(TBLIDXB3):
- case OE_RR_X1(WH64):
default:
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
reg_names[dest], reg_names[srca]);
- return TILEGX_EXCP_NONE;
+ return ret;
}
static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 23/33] target-tilegx: Handle bitfield instructions
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (20 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 22/33] target-tilegx: Implement system and memory management instructions Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-30 13:31 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 24/33] target-tilegx: Handle shift instructions Richard Henderson
` (10 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 5bdc8be..6be751b 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1128,13 +1128,87 @@ static TileExcp gen_bf_opcode_x0(DisasContext *dc, unsigned ext,
unsigned dest, unsigned srca,
unsigned bfs, unsigned bfe)
{
+ TCGv tdest = dest_gr(dc, dest);
+ TCGv tsrca = load_gr(dc, srca);
+ TCGv tsrcd;
+ int len;
const char *mnemonic;
+ /* The bitfield is either between E and S inclusive,
+ or up from S and down from E inclusive. */
+ if (bfs <= bfe) {
+ len = bfe - bfs + 1;
+ } else {
+ len = (64 - bfs) + (bfe + 1);
+ }
+
switch (ext) {
case BFEXTU_BF_OPCODE_X0:
+ if (bfs == 0 && bfe == 7) {
+ tcg_gen_ext8u_tl(tdest, tsrca);
+ } else if (bfs == 0 && bfe == 15) {
+ tcg_gen_ext16u_tl(tdest, tsrca);
+ } else if (bfs == 0 && bfe == 31) {
+ tcg_gen_ext32u_tl(tdest, tsrca);
+ } else {
+ int rol = 63 - bfe;
+ if (bfs <= bfe) {
+ tcg_gen_shli_tl(tdest, tsrca, rol);
+ } else {
+ tcg_gen_rotli_tl(tdest, tsrca, rol);
+ }
+ tcg_gen_shri_tl(tdest, tdest, (bfs + rol) & 63);
+ }
+ mnemonic = "bfextu";
+ break;
+
case BFEXTS_BF_OPCODE_X0:
+ if (bfs == 0 && bfe == 7) {
+ tcg_gen_ext8s_tl(tdest, tsrca);
+ } else if (bfs == 0 && bfe == 15) {
+ tcg_gen_ext16s_tl(tdest, tsrca);
+ } else if (bfs == 0 && bfe == 31) {
+ tcg_gen_ext32s_tl(tdest, tsrca);
+ } else {
+ int rol = 63 - bfe;
+ if (bfs <= bfe) {
+ tcg_gen_shli_tl(tdest, tsrca, rol);
+ } else {
+ tcg_gen_rotli_tl(tdest, tsrca, rol);
+ }
+ tcg_gen_sari_tl(tdest, tdest, (bfs + rol) & 63);
+ }
+ mnemonic = "bfexts";
+ break;
+
case BFINS_BF_OPCODE_X0:
+ tsrcd = load_gr(dc, dest);
+ if (bfs <= bfe) {
+ tcg_gen_deposit_tl(tdest, tsrcd, tsrca, bfs, len);
+ } else {
+ tcg_gen_rotri_tl(tdest, tsrcd, bfs);
+ tcg_gen_deposit_tl(tdest, tdest, tsrca, 0, len);
+ tcg_gen_rotli_tl(tdest, tdest, bfs);
+ }
+ mnemonic = "bfins";
+ break;
+
case MM_BF_OPCODE_X0:
+ tsrcd = load_gr(dc, dest);
+ if (bfs == 0) {
+ tcg_gen_deposit_tl(tdest, tsrca, tsrcd, 0, len);
+ } else {
+ uint64_t mask = len == 64 ? -1 : rol64((1ULL << len) - 1, bfs);
+ TCGv tmp = tcg_const_tl(mask);
+
+ tcg_gen_and_tl(tdest, tsrcd, tmp);
+ tcg_gen_andc_tl(tmp, tsrca, tmp);
+ tcg_gen_or_tl(tdest, tdest, tmp);
+ tcg_temp_free(tmp);
+ }
+ mnemonic = "mm";
+ break;
+
default:
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
}
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 24/33] target-tilegx: Handle shift instructions
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (21 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 23/33] target-tilegx: Handle bitfield instructions Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-30 13:38 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 25/33] target-tilegx: Handle conditional move instructions Richard Henderson
` (9 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 57 +++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 55 insertions(+), 2 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 6be751b..4e6d577 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -474,6 +474,7 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
TCGv tdest = dest_gr(dc, dest);
TCGv tsrca = load_gr(dc, srca);
TCGv tsrcb = load_gr(dc, srcb);
+ TCGv t0;
const char *mnemonic;
switch (opext) {
@@ -666,7 +667,10 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(ROTL, 0, X1):
case OE_RRR(ROTL, 6, Y0):
case OE_RRR(ROTL, 6, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ tcg_gen_andi_tl(tdest, tsrcb, 63);
+ tcg_gen_rotl_tl(tdest, tsrca, tdest);
+ mnemonic = "torl";
+ break;
case OE_RRR(SHL1ADDX, 0, X0):
case OE_RRR(SHL1ADDX, 0, X1):
case OE_RRR(SHL1ADDX, 7, Y0):
@@ -720,21 +724,45 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
break;
case OE_RRR(SHLX, 0, X0):
case OE_RRR(SHLX, 0, X1):
+ tcg_gen_andi_tl(tdest, tsrcb, 31);
+ tcg_gen_shl_tl(tdest, tsrca, tdest);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "shlx";
+ break;
case OE_RRR(SHL, 0, X0):
case OE_RRR(SHL, 0, X1):
case OE_RRR(SHL, 6, Y0):
case OE_RRR(SHL, 6, Y1):
+ tcg_gen_andi_tl(tdest, tsrcb, 63);
+ tcg_gen_shl_tl(tdest, tsrca, tdest);
+ mnemonic = "shl";
+ break;
case OE_RRR(SHRS, 0, X0):
case OE_RRR(SHRS, 0, X1):
case OE_RRR(SHRS, 6, Y0):
case OE_RRR(SHRS, 6, Y1):
+ tcg_gen_andi_tl(tdest, tsrcb, 63);
+ tcg_gen_sar_tl(tdest, tsrca, tdest);
+ mnemonic = "shrs";
+ break;
case OE_RRR(SHRUX, 0, X0):
case OE_RRR(SHRUX, 0, X1):
+ t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, tsrcb, 31);
+ tcg_gen_ext32u_tl(tdest, tsrca);
+ tcg_gen_shl_tl(tdest, tdest, t0);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ tcg_temp_free(t0);
+ mnemonic = "shrux";
+ break;
case OE_RRR(SHRU, 0, X0):
case OE_RRR(SHRU, 0, X1):
case OE_RRR(SHRU, 6, Y0):
case OE_RRR(SHRU, 6, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ tcg_gen_andi_tl(tdest, tsrcb, 63);
+ tcg_gen_shr_tl(tdest, tsrca, tdest);
+ mnemonic = "shru";
+ break;
case OE_RRR(SHUFFLEBYTES, 0, X0):
gen_helper_shufflebytes(tdest, load_gr(dc, dest), tsrca, tsrca);
mnemonic = "shufflebytes";
@@ -1068,22 +1096,46 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
case OE_SH(ROTLI, X1):
case OE_SH(ROTLI, Y0):
case OE_SH(ROTLI, Y1):
+ tcg_gen_rotli_tl(tdest, tsrca, imm);
+ mnemonic = "rotli";
+ break;
case OE_SH(SHLI, X0):
case OE_SH(SHLI, X1):
case OE_SH(SHLI, Y0):
case OE_SH(SHLI, Y1):
+ tcg_gen_shli_tl(tdest, tsrca, imm);
+ mnemonic = "shli";
+ break;
case OE_SH(SHLXI, X0):
case OE_SH(SHLXI, X1):
+ tcg_gen_shli_tl(tdest, tsrca, imm & 31);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "shlxi";
+ break;
case OE_SH(SHRSI, X0):
case OE_SH(SHRSI, X1):
case OE_SH(SHRSI, Y0):
case OE_SH(SHRSI, Y1):
+ tcg_gen_sari_tl(tdest, tsrca, imm);
+ mnemonic = "shrsi";
+ break;
case OE_SH(SHRUI, X0):
case OE_SH(SHRUI, X1):
case OE_SH(SHRUI, Y0):
case OE_SH(SHRUI, Y1):
+ tcg_gen_shri_tl(tdest, tsrca, imm);
+ mnemonic = "shrui";
+ break;
case OE_SH(SHRUXI, X0):
case OE_SH(SHRUXI, X1):
+ if ((imm & 31) == 0) {
+ tcg_gen_ext32s_tl(tdest, tsrca);
+ } else {
+ tcg_gen_ext32u_tl(tdest, tsrca);
+ tcg_gen_shli_tl(tdest, tdest, imm & 31);
+ }
+ mnemonic = "shlxi";
+ break;
case OE_SH(V1SHLI, X0):
case OE_SH(V1SHLI, X1):
case OE_SH(V1SHRSI, X0):
@@ -1096,6 +1148,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
case OE_SH(V2SHRSI, X1):
case OE_SH(V2SHRUI, X0):
case OE_SH(V2SHRUI, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE(ADDLI_OPCODE_X0, 0, X0):
case OE(ADDLI_OPCODE_X1, 0, X1):
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 25/33] target-tilegx: Handle conditional move instructions
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (22 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 24/33] target-tilegx: Handle shift instructions Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-30 13:40 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 26/33] target-tilegx: Handle scalar multiply instructions Richard Henderson
` (8 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 4e6d577..b504ae3 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -507,9 +507,16 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
break;
case OE_RRR(CMOVEQZ, 0, X0):
case OE_RRR(CMOVEQZ, 4, Y0):
+ tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, load_zero(dc),
+ tsrcb, load_gr(dc, dest));
+ mnemonic = "cmoveqz";
+ break;
case OE_RRR(CMOVNEZ, 0, X0):
case OE_RRR(CMOVNEZ, 4, Y0):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, load_zero(dc),
+ tsrcb, load_gr(dc, dest));
+ mnemonic = "cmovnez";
+ break;
case OE_RRR(CMPEQ, 0, X0):
case OE_RRR(CMPEQ, 0, X1):
case OE_RRR(CMPEQ, 3, Y0):
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 26/33] target-tilegx: Handle scalar multiply instructions
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (23 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 25/33] target-tilegx: Handle conditional move instructions Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-30 13:46 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 27/33] target-tilegx: Handle mask instructions Richard Henderson
` (7 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 112 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 112 insertions(+)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index b504ae3..51ee158 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -206,6 +206,38 @@ static void gen_dblalign(TCGv tdest, TCGv tsrcd, TCGv tsrca, TCGv tsrcb)
tcg_temp_free(t0);
}
+#define LU 0
+#define LS 1
+#define HU 2
+#define HS 3
+
+static void gen_ext_half(TCGv d, TCGv s, int h)
+{
+ switch (h) {
+ case LU:
+ tcg_gen_ext32u_tl(d, s);
+ break;
+ case LS:
+ tcg_gen_ext32s_tl(d, s);
+ break;
+ case HU:
+ tcg_gen_shri_tl(d, s, 32);
+ break;
+ case HS:
+ tcg_gen_sari_tl(d, s, 32);
+ break;
+ }
+}
+
+static void gen_mul_half(TCGv tdest, TCGv tsrca, TCGv tsrcb, int ha, int hb)
+{
+ TCGv t = tcg_temp_new();
+ gen_ext_half(t, tsrca, ha);
+ gen_ext_half(tdest, tsrcb, hb);
+ tcg_gen_mul_tl(tdest, tdest, t);
+ tcg_temp_free(t);
+}
+
static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,
unsigned srcb, TCGMemOp memop, const char *name)
{
@@ -619,38 +651,118 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(MNZ, 0, X1):
case OE_RRR(MNZ, 4, Y0):
case OE_RRR(MNZ, 4, Y1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(MULAX, 0, X0):
case OE_RRR(MULAX, 3, Y0):
+ tcg_gen_mul_tl(tdest, tsrca, tsrcb);
+ tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "mulax";
+ break;
case OE_RRR(MULA_HS_HS, 0, X0):
case OE_RRR(MULA_HS_HS, 9, Y0):
+ gen_mul_half(tdest, tsrca, tsrcb, HS, HS);
+ tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
+ mnemonic = "mula_hs_hs";
+ break;
case OE_RRR(MULA_HS_HU, 0, X0):
+ gen_mul_half(tdest, tsrca, tsrcb, HS, HU);
+ tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
+ mnemonic = "mula_hs_hu";
+ break;
case OE_RRR(MULA_HS_LS, 0, X0):
+ gen_mul_half(tdest, tsrca, tsrcb, HS, LS);
+ tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
+ mnemonic = "mula_hs_ls";
+ break;
case OE_RRR(MULA_HS_LU, 0, X0):
+ gen_mul_half(tdest, tsrca, tsrcb, HS, LU);
+ tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
+ mnemonic = "mula_hs_lu";
+ break;
case OE_RRR(MULA_HU_HU, 0, X0):
case OE_RRR(MULA_HU_HU, 9, Y0):
+ gen_mul_half(tdest, tsrca, tsrcb, HU, HU);
+ tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
+ mnemonic = "mula_hu_hu";
+ break;
case OE_RRR(MULA_HU_LS, 0, X0):
+ gen_mul_half(tdest, tsrca, tsrcb, HU, LS);
+ tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
+ mnemonic = "mula_hu_ls";
+ break;
case OE_RRR(MULA_HU_LU, 0, X0):
+ gen_mul_half(tdest, tsrca, tsrcb, HU, LU);
+ tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
+ mnemonic = "mula_hu_lu";
+ break;
case OE_RRR(MULA_LS_LS, 0, X0):
case OE_RRR(MULA_LS_LS, 9, Y0):
+ gen_mul_half(tdest, tsrca, tsrcb, LS, LS);
+ tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
+ mnemonic = "mula_ls_ls";
+ break;
case OE_RRR(MULA_LS_LU, 0, X0):
+ gen_mul_half(tdest, tsrca, tsrcb, LS, LU);
+ tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
+ mnemonic = "mula_ls_lu";
+ break;
case OE_RRR(MULA_LU_LU, 0, X0):
case OE_RRR(MULA_LU_LU, 9, Y0):
+ gen_mul_half(tdest, tsrca, tsrcb, LU, LU);
+ tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
+ mnemonic = "mula_lu_lu";
+ break;
case OE_RRR(MULX, 0, X0):
case OE_RRR(MULX, 3, Y0):
+ tcg_gen_mul_tl(tdest, tsrca, tsrcb);
+ tcg_gen_ext32s_tl(tdest, tdest);
+ mnemonic = "mulx";
+ break;
case OE_RRR(MUL_HS_HS, 0, X0):
case OE_RRR(MUL_HS_HS, 8, Y0):
+ gen_mul_half(tdest, tsrca, tsrcb, HS, HS);
+ mnemonic = "mul_hs_hs";
+ break;
case OE_RRR(MUL_HS_HU, 0, X0):
+ gen_mul_half(tdest, tsrca, tsrcb, HS, HU);
+ mnemonic = "mul_hs_hu";
+ break;
case OE_RRR(MUL_HS_LS, 0, X0):
+ gen_mul_half(tdest, tsrca, tsrcb, HS, LS);
+ mnemonic = "mul_hs_ls";
+ break;
case OE_RRR(MUL_HS_LU, 0, X0):
+ gen_mul_half(tdest, tsrca, tsrcb, HS, LU);
+ mnemonic = "mul_hs_lu";
+ break;
case OE_RRR(MUL_HU_HU, 0, X0):
case OE_RRR(MUL_HU_HU, 8, Y0):
+ gen_mul_half(tdest, tsrca, tsrcb, HU, HU);
+ mnemonic = "mul_hu_hu";
+ break;
case OE_RRR(MUL_HU_LS, 0, X0):
+ gen_mul_half(tdest, tsrca, tsrcb, HU, LS);
+ mnemonic = "mul_hu_ls";
+ break;
case OE_RRR(MUL_HU_LU, 0, X0):
+ gen_mul_half(tdest, tsrca, tsrcb, HU, LU);
+ mnemonic = "mul_hu_lu";
+ break;
case OE_RRR(MUL_LS_LS, 0, X0):
case OE_RRR(MUL_LS_LS, 8, Y0):
+ gen_mul_half(tdest, tsrca, tsrcb, LS, LS);
+ mnemonic = "mul_ls_ls";
+ break;
case OE_RRR(MUL_LS_LU, 0, X0):
+ gen_mul_half(tdest, tsrca, tsrcb, LS, LU);
+ mnemonic = "mul_ls_lu";
+ break;
case OE_RRR(MUL_LU_LU, 0, X0):
case OE_RRR(MUL_LU_LU, 8, Y0):
+ gen_mul_half(tdest, tsrca, tsrcb, LU, LU);
+ mnemonic = "mul_lu_lu";
+ break;
case OE_RRR(MZ, 0, X0):
case OE_RRR(MZ, 0, X1):
case OE_RRR(MZ, 4, Y0):
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 27/33] target-tilegx: Handle mask instructions
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (24 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 26/33] target-tilegx: Handle scalar multiply instructions Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-30 13:52 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 28/33] target-tilegx: Handle v1cmpeq, v1cmpne Richard Henderson
` (6 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 51ee158..af4b34a 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -647,11 +647,15 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(FSINGLE_MUL2, 0, X0):
case OE_RRR(FSINGLE_PACK2, 0, X0):
case OE_RRR(FSINGLE_SUB1, 0, X0):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(MNZ, 0, X0):
case OE_RRR(MNZ, 0, X1):
case OE_RRR(MNZ, 4, Y0):
case OE_RRR(MNZ, 4, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ t0 = load_zero(dc);
+ tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, t0, tsrcb, t0);
+ mnemonic = "mnz";
+ break;
case OE_RRR(MULAX, 0, X0):
case OE_RRR(MULAX, 3, Y0):
tcg_gen_mul_tl(tdest, tsrca, tsrcb);
@@ -767,7 +771,10 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(MZ, 0, X1):
case OE_RRR(MZ, 4, Y0):
case OE_RRR(MZ, 4, Y1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ t0 = load_zero(dc);
+ tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, t0, tsrcb, t0);
+ mnemonic = "mz";
+ break;
case OE_RRR(NOR, 0, X0):
case OE_RRR(NOR, 0, X1):
case OE_RRR(NOR, 5, Y0):
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 28/33] target-tilegx: Handle v1cmpeq, v1cmpne
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (25 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 27/33] target-tilegx: Handle mask instructions Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-30 15:11 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 29/33] target-tilegx: Handle mtspr, mfspr Richard Henderson
` (5 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index af4b34a..1224a8e 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -93,6 +93,8 @@ typedef struct {
#define OE_IM(E,XY) OE(IMM8_OPCODE_##XY, E##_IMM8_OPCODE_##XY, XY)
#define OE_SH(E,XY) OE(SHIFT_OPCODE_##XY, E##_SHIFT_OPCODE_##XY, XY)
+#define V1_IMM(X) (((X) & 0xff) * 0x0101010101010101ull)
+
static void gen_exception(DisasContext *dc, TileExcp num)
{
@@ -238,6 +240,41 @@ static void gen_mul_half(TCGv tdest, TCGv tsrca, TCGv tsrcb, int ha, int hb)
tcg_temp_free(t);
}
+/* Equality comparison with zero can be done quickly and efficiently. */
+static void gen_v1cmpeq0(TCGv v)
+{
+ TCGv m = tcg_const_tl(V1_IMM(0x7f));
+ TCGv c = tcg_temp_new();
+
+ /* ~(((a & m) + m) | m | a). Sets the msb for each byte == 0. */
+ tcg_gen_and_tl(c, v, m);
+ tcg_gen_add_tl(c, c, m);
+ tcg_gen_or_tl(c, c, m);
+ tcg_gen_nor_tl(c, c, v);
+ tcg_temp_free(m);
+
+ /* Shift the msb down to form the lsb boolean result. */
+ tcg_gen_shri_tl(v, c, 7);
+ tcg_temp_free(c);
+}
+
+static void gen_v1cmpne0(TCGv v)
+{
+ TCGv m = tcg_const_tl(V1_IMM(0x7f));
+ TCGv c = tcg_temp_new();
+
+ /* (((a & m) + m) | a) & ~m. Sets the msb for each byte != 0. */
+ tcg_gen_and_tl(c, v, m);
+ tcg_gen_add_tl(c, c, m);
+ tcg_gen_or_tl(c, c, v);
+ tcg_gen_andc_tl(c, c, m);
+ tcg_temp_free(m);
+
+ /* Shift the msb down to form the lsb boolean result. */
+ tcg_gen_shri_tl(v, c, 7);
+ tcg_temp_free(c);
+}
+
static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,
unsigned srcb, TCGMemOp memop, const char *name)
{
@@ -919,8 +956,13 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(V1ADD, 0, X1):
case OE_RRR(V1ADIFFU, 0, X0):
case OE_RRR(V1AVGU, 0, X0):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V1CMPEQ, 0, X0):
case OE_RRR(V1CMPEQ, 0, X1):
+ tcg_gen_xor_tl(tdest, tsrca, tsrcb);
+ gen_v1cmpeq0(tdest);
+ mnemonic = "v1cmpeq";
+ break;
case OE_RRR(V1CMPLES, 0, X0):
case OE_RRR(V1CMPLES, 0, X1):
case OE_RRR(V1CMPLEU, 0, X0):
@@ -929,8 +971,13 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(V1CMPLTS, 0, X1):
case OE_RRR(V1CMPLTU, 0, X0):
case OE_RRR(V1CMPLTU, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V1CMPNE, 0, X0):
case OE_RRR(V1CMPNE, 0, X1):
+ tcg_gen_xor_tl(tdest, tsrca, tsrcb);
+ gen_v1cmpne0(tdest);
+ mnemonic = "v1cmpne";
+ break;
case OE_RRR(V1DDOTPUA, 0, X0):
case OE_RRR(V1DDOTPUSA, 0, X0):
case OE_RRR(V1DDOTPUS, 0, X0):
@@ -1191,6 +1238,10 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
case OE_IM(V1ADDI, X1):
case OE_IM(V1CMPEQI, X0):
case OE_IM(V1CMPEQI, X1):
+ tcg_gen_xori_tl(tdest, tsrca, V1_IMM(imm));
+ gen_v1cmpeq0(tdest);
+ mnemonic = "v1cmpeqi";
+ break;
case OE_IM(V1CMPLTSI, X0):
case OE_IM(V1CMPLTSI, X1):
case OE_IM(V1CMPLTUI, X0):
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 29/33] target-tilegx: Handle mtspr, mfspr
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (26 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 28/33] target-tilegx: Handle v1cmpeq, v1cmpne Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-30 15:18 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions Richard Henderson
` (4 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 76 +++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 73 insertions(+), 3 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 1224a8e..210e912 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -24,6 +24,7 @@
#include "tcg-op.h"
#include "exec/cpu_ldst.h"
#include "opcode_tilegx.h"
+#include "spr_def_64.h"
#define FMT64X "%016" PRIx64
@@ -1226,9 +1227,6 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
mnemonic = "ldna_add";
break;
- case OE_IM(MFSPR, X1):
- case OE_IM(MTSPR, X1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_IM(ORI, X0):
case OE_IM(ORI, X1):
tcg_gen_ori_tl(tdest, tsrca, imm);
@@ -1528,6 +1526,74 @@ static TileExcp gen_jump_opcode_x1(DisasContext *dc, unsigned ext, int off)
return TILEGX_EXCP_NONE;
}
+typedef struct {
+ const char *name;
+ intptr_t offset;
+ void (*get)(TCGv, TCGv_ptr);
+ void (*put)(TCGv_ptr, TCGv);
+} TileSPR;
+
+static const TileSPR *find_spr(unsigned spr)
+{
+ /* Allow the compiler to construct the binary search tree. */
+#define D(N, O, G, P) \
+ case SPR_##N: { static const TileSPR x = { #N, O, G, P }; return &x; }
+
+ switch (spr) {
+ D(CMPEXCH_VALUE,
+ offsetof(CPUTLGState, spregs[TILEGX_SPR_CMPEXCH]), 0, 0)
+ D(SIM_CONTROL,
+ offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0)
+ D(INTERRUPT_CRITICAL_SECTION,
+ offsetof(CPUTLGState, spregs[TILEGX_SPR_SIM_CONTROL]), 0, 0)
+ }
+
+#undef D
+
+ qemu_log_mask(LOG_UNIMP, "UNIMP SPR %u\n", spr);
+ return NULL;
+}
+
+static TileExcp gen_mtspr_x1(DisasContext *dc, unsigned spr, unsigned srca)
+{
+ const TileSPR *def = find_spr(spr);
+ TCGv tsrca;
+
+ if (def == NULL) {
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr spr[%u], %s", spr, reg_names[srca]);
+ return TILEGX_EXCP_OPCODE_UNKNOWN;
+ }
+
+ tsrca = load_gr(dc, srca);
+ if (def->put) {
+ def->put(cpu_env, tsrca);
+ } else {
+ tcg_gen_st_tl(tsrca, cpu_env, def->offset);
+ }
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, %s", def->name, reg_names[srca]);
+ return TILEGX_EXCP_NONE;
+}
+
+static TileExcp gen_mfspr_x1(DisasContext *dc, unsigned dest, unsigned spr)
+{
+ const TileSPR *def = find_spr(spr);
+ TCGv tdest;
+
+ if (def == NULL) {
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, spr[%u]", reg_names[dest], spr);
+ return TILEGX_EXCP_OPCODE_UNKNOWN;
+ }
+
+ tdest = dest_gr(dc, dest);
+ if (def->get) {
+ def->get(tdest, cpu_env);
+ } else {
+ tcg_gen_ld_tl(tdest, cpu_env, def->offset);
+ }
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "mfspr %s, %s", reg_names[dest], def->name);
+ return TILEGX_EXCP_NONE;
+}
+
static TileExcp decode_y0(DisasContext *dc, tilegx_bundle_bits bundle)
{
unsigned opc = get_Opcode_Y0(bundle);
@@ -1782,6 +1848,10 @@ static TileExcp decode_x1(DisasContext *dc, tilegx_bundle_bits bundle)
return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEQ, "stnt_add");
case ST_ADD_IMM8_OPCODE_X1:
return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEQ, "st_add");
+ case MFSPR_IMM8_OPCODE_X1:
+ return gen_mfspr_x1(dc, dest, get_MF_Imm14_X1(bundle));
+ case MTSPR_IMM8_OPCODE_X1:
+ return gen_mtspr_x1(dc, get_MT_Imm14_X1(bundle), srca);
}
imm = (int8_t)get_Imm8_X1(bundle);
return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (27 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 29/33] target-tilegx: Handle mtspr, mfspr Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-25 4:15 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 31/33] target-tilegx: Handle v4int_l/h Richard Henderson
` (3 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 210e912..2a0798a 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -180,6 +180,19 @@ static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
tcg_temp_free(t0);
}
+static void gen_atomic_excp(DisasContext *dc, unsigned dest, unsigned srca,
+ unsigned srcb, TileExcp excp)
+{
+#ifdef CONFIG_USER_ONLY
+ TCGv_i32 t = tcg_const_i32((dest << 16) | (srca << 8) | srcb);
+ tcg_gen_st_i32(t, cpu_env, offsetof(CPUTLGState, excparam));
+ tcg_temp_free_i32(t);
+ gen_exception(dc, excp);
+#else
+ gen_exception(dc, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
+#endif
+}
+
static void gen_dblaligni(TCGv tdest, TCGv tsrca, TCGv tsrcb, int shr)
{
TCGv t0 = tcg_temp_new();
@@ -595,8 +608,13 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
mnemonic = "cmpeq";
break;
case OE_RRR(CMPEXCH4, 0, X1):
+ gen_atomic_excp(dc, dest, srca, srcb, TILEGX_EXCP_OPCODE_CMPEXCH4);
+ mnemonic = "cmpexch4";
+ break;
case OE_RRR(CMPEXCH, 0, X1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ gen_atomic_excp(dc, dest, srca, srcb, TILEGX_EXCP_OPCODE_CMPEXCH);
+ mnemonic = "cmpexch";
+ break;
case OE_RRR(CMPLES, 0, X0):
case OE_RRR(CMPLES, 0, X1):
case OE_RRR(CMPLES, 2, Y0):
@@ -662,7 +680,13 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
mnemonic = "dblalign";
break;
case OE_RRR(EXCH4, 0, X1):
+ gen_atomic_excp(dc, dest, srca, srcb, TILEGX_EXCP_OPCODE_EXCH4);
+ mnemonic = "exch4";
+ break;
case OE_RRR(EXCH, 0, X1):
+ gen_atomic_excp(dc, dest, srca, srcb, TILEGX_EXCP_OPCODE_EXCH);
+ mnemonic = "exch";
+ break;
case OE_RRR(FDOUBLE_ADDSUB, 0, X0):
case OE_RRR(FDOUBLE_ADD_FLAGS, 0, X0):
case OE_RRR(FDOUBLE_MUL_FLAGS, 0, X0):
@@ -672,13 +696,37 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(FDOUBLE_UNPACK_MAX, 0, X0):
case OE_RRR(FDOUBLE_UNPACK_MIN, 0, X0):
case OE_RRR(FETCHADD4, 0, X1):
+ gen_atomic_excp(dc, dest, srca, srcb, TILEGX_EXCP_OPCODE_FETCHADD4);
+ mnemonic = "fetchadd4";
+ break;
case OE_RRR(FETCHADDGEZ4, 0, X1):
+ gen_atomic_excp(dc, dest, srca, srcb, TILEGX_EXCP_OPCODE_FETCHADDGEZ4);
+ mnemonic = "fetchaddgez4";
+ break;
case OE_RRR(FETCHADDGEZ, 0, X1):
+ gen_atomic_excp(dc, dest, srca, srcb, TILEGX_EXCP_OPCODE_FETCHADDGEZ);
+ mnemonic = "fetchaddgez";
+ break;
case OE_RRR(FETCHADD, 0, X1):
+ gen_atomic_excp(dc, dest, srca, srcb, TILEGX_EXCP_OPCODE_FETCHADD);
+ mnemonic = "fetchadd";
+ break;
case OE_RRR(FETCHAND4, 0, X1):
+ gen_atomic_excp(dc, dest, srca, srcb, TILEGX_EXCP_OPCODE_FETCHAND4);
+ mnemonic = "fetchand4";
+ break;
case OE_RRR(FETCHAND, 0, X1):
+ gen_atomic_excp(dc, dest, srca, srcb, TILEGX_EXCP_OPCODE_FETCHAND);
+ mnemonic = "fetchand";
+ break;
case OE_RRR(FETCHOR4, 0, X1):
+ gen_atomic_excp(dc, dest, srca, srcb, TILEGX_EXCP_OPCODE_FETCHOR4);
+ mnemonic = "fetchor4";
+ break;
case OE_RRR(FETCHOR, 0, X1):
+ gen_atomic_excp(dc, dest, srca, srcb, TILEGX_EXCP_OPCODE_FETCHOR);
+ mnemonic = "fetchor";
+ break;
case OE_RRR(FSINGLE_ADD1, 0, X0):
case OE_RRR(FSINGLE_ADDSUB2, 0, X0):
case OE_RRR(FSINGLE_MUL1, 0, X0):
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 31/33] target-tilegx: Handle v4int_l/h
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (28 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-30 15:20 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 32/33] target-tilegx: Handle v1shli, v1shrui Richard Henderson
` (2 subsequent siblings)
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 2a0798a..e922aee 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1125,10 +1125,18 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(V4ADDSC, 0, X1):
case OE_RRR(V4ADD, 0, X0):
case OE_RRR(V4ADD, 0, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V4INT_H, 0, X0):
case OE_RRR(V4INT_H, 0, X1):
+ tcg_gen_shri_tl(tdest, tsrcb, 32);
+ tcg_gen_deposit_tl(tdest, tsrca, tdest, 0, 32);
+ mnemonic = "v4int_h";
+ break;
case OE_RRR(V4INT_L, 0, X0):
case OE_RRR(V4INT_L, 0, X1):
+ tcg_gen_deposit_tl(tdest, tsrcb, tsrca, 32, 32);
+ mnemonic = "v4int_l";
+ break;
case OE_RRR(V4PACKSC, 0, X0):
case OE_RRR(V4PACKSC, 0, X1):
case OE_RRR(V4SHLSC, 0, X0):
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 32/33] target-tilegx: Handle v1shli, v1shrui
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (29 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 31/33] target-tilegx: Handle v4int_l/h Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-30 15:23 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 33/33] target-tilegx: Handle v1shl, v1shru, v1shrs Richard Henderson
[not found] ` <55DB96D7.9000105@hotmail.com>
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/translate.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index e922aee..e417c2a 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1175,6 +1175,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
TCGv tsrca = load_gr(dc, srca);
const char *mnemonic;
TCGMemOp memop;
+ int i2, i3;
switch (opext) {
case OE(ADDI_OPCODE_Y0, 0, Y0):
@@ -1369,10 +1370,23 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
break;
case OE_SH(V1SHLI, X0):
case OE_SH(V1SHLI, X1):
+ i2 = imm & 7;
+ i3 = 0xff >> i2;
+ tcg_gen_andi_tl(tdest, tsrca, V1_IMM(i3));
+ tcg_gen_shli_tl(tdest, tdest, i2);
+ mnemonic = "v1shli";
+ break;
case OE_SH(V1SHRSI, X0):
case OE_SH(V1SHRSI, X1):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_SH(V1SHRUI, X0):
case OE_SH(V1SHRUI, X1):
+ i2 = imm & 7;
+ i3 = (0xff << i2) & 0xff;
+ tcg_gen_andi_tl(tdest, tsrca, V1_IMM(i3));
+ tcg_gen_shri_tl(tdest, tdest, i2);
+ mnemonic = "v1shrui";
+ break;
case OE_SH(V2SHLI, X0):
case OE_SH(V2SHLI, X1):
case OE_SH(V2SHRSI, X0):
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Qemu-devel] [PATCH v14 33/33] target-tilegx: Handle v1shl, v1shru, v1shrs
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
` (30 preceding siblings ...)
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 32/33] target-tilegx: Handle v1shli, v1shrui Richard Henderson
@ 2015-08-24 16:17 ` Richard Henderson
2015-08-30 15:28 ` Peter Maydell
[not found] ` <55DB96D7.9000105@hotmail.com>
32 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:17 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-tilegx/Makefile.objs | 2 +-
target-tilegx/helper.h | 4 +++
target-tilegx/simd_helper.c | 63 +++++++++++++++++++++++++++++++++++++++++++++
target-tilegx/translate.c | 17 +++++++++++-
4 files changed, 84 insertions(+), 2 deletions(-)
create mode 100644 target-tilegx/simd_helper.c
diff --git a/target-tilegx/Makefile.objs b/target-tilegx/Makefile.objs
index 8b3dc76..0db778f 100644
--- a/target-tilegx/Makefile.objs
+++ b/target-tilegx/Makefile.objs
@@ -1 +1 @@
-obj-y += cpu.o translate.o helper.o
+obj-y += cpu.o translate.o helper.o simd_helper.o
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
index 644d313..766f5f2 100644
--- a/target-tilegx/helper.h
+++ b/target-tilegx/helper.h
@@ -4,3 +4,7 @@ DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(revbits, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
+
+DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c
new file mode 100644
index 0000000..7670d4a
--- /dev/null
+++ b/target-tilegx/simd_helper.c
@@ -0,0 +1,63 @@
+/*
+ * QEMU TILE-Gx helpers
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu.h"
+#include "qemu-common.h"
+#include "exec/helper-proto.h"
+
+
+uint64_t helper_v1shl(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0;
+ int i;
+
+ for (i = 0; i < 64; i += 8) {
+ uint64_t m = 0xffULL << i;
+ uint64_t be = (b >> i) & 7;
+ r |= ((a & m) << be) & m;
+ }
+ return r;
+}
+
+uint64_t helper_v1shru(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0;
+ int i;
+
+ for (i = 0; i < 64; i += 8) {
+ uint64_t m = 0xffULL << i;
+ uint64_t be = (b >> i) & 7;
+ r |= ((a & m) >> be) & m;
+ }
+ return r;
+}
+
+uint64_t helper_v1shrs(uint64_t a, uint64_t b)
+{
+ uint64_t r = 0;
+ int i;
+
+ for (i = 0; i < 64; i += 8) {
+ uint64_t ae = (int8_t)(a >> i);
+ uint64_t be = (b >> i) & 7;
+ r |= ((ae >> be) & 0xff) << i;
+ }
+ return r;
+}
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index e417c2a..f841553 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1054,12 +1054,22 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
case OE_RRR(V1MZ, 0, X1):
case OE_RRR(V1SADAU, 0, X0):
case OE_RRR(V1SADU, 0, X0):
+ return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
case OE_RRR(V1SHL, 0, X0):
case OE_RRR(V1SHL, 0, X1):
+ gen_helper_v1shl(tdest, tsrca, tsrcb);
+ mnemonic = "v1shl";
+ break;
case OE_RRR(V1SHRS, 0, X0):
case OE_RRR(V1SHRS, 0, X1):
+ gen_helper_v1shrs(tdest, tsrca, tsrcb);
+ mnemonic = "v1shrs";
+ break;
case OE_RRR(V1SHRU, 0, X0):
case OE_RRR(V1SHRU, 0, X1):
+ gen_helper_v1shru(tdest, tsrca, tsrcb);
+ mnemonic = "v1shru";
+ break;
case OE_RRR(V1SUBUC, 0, X0):
case OE_RRR(V1SUBUC, 0, X1):
case OE_RRR(V1SUB, 0, X0):
@@ -1176,6 +1186,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
const char *mnemonic;
TCGMemOp memop;
int i2, i3;
+ TCGv t0;
switch (opext) {
case OE(ADDI_OPCODE_Y0, 0, Y0):
@@ -1378,7 +1389,11 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
break;
case OE_SH(V1SHRSI, X0):
case OE_SH(V1SHRSI, X1):
- return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ t0 = tcg_const_tl(V1_IMM(imm & 7));
+ gen_helper_v1shrs(tdest, tsrca, t0);
+ tcg_temp_free(t0);
+ mnemonic = "v1shrsi";
+ break;
case OE_SH(V1SHRUI, X0):
case OE_SH(V1SHRUI, X1):
i2 = imm & 7;
--
2.4.3
^ permalink raw reply related [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 07/33] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 07/33] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 Richard Henderson
@ 2015-08-24 16:29 ` Peter Maydell
2015-08-24 16:43 ` Richard Henderson
2015-08-26 17:11 ` Chris Metcalf
2015-08-29 14:30 ` Peter Maydell
2 siblings, 1 reply; 80+ messages in thread
From: Peter Maydell @ 2015-08-24 16:29 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> An obvious typo in the mnemonic here.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/opcode_tilegx.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-tilegx/opcode_tilegx.h b/target-tilegx/opcode_tilegx.h
> index 3b8bf4f..989436d 100644
> --- a/target-tilegx/opcode_tilegx.h
> +++ b/target-tilegx/opcode_tilegx.h
> @@ -1015,7 +1015,7 @@ enum
> LD_UNARY_OPCODE_X1 = 29,
> LNK_UNARY_OPCODE_X1 = 30,
> LNK_UNARY_OPCODE_Y1 = 14,
> - LWNA_ADD_IMM8_OPCODE_X1 = 21,
> + LDNA_ADD_IMM8_OPCODE_X1 = 21,
> MFSPR_IMM8_OPCODE_X1 = 22,
> MF_UNARY_OPCODE_X1 = 31,
> MM_BF_OPCODE_X0 = 7,
> --
> 2.4.3
Should we feed this fix and the one in patch 6 back to
the kernel?
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 07/33] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1
2015-08-24 16:29 ` Peter Maydell
@ 2015-08-24 16:43 ` Richard Henderson
0 siblings, 0 replies; 80+ messages in thread
From: Richard Henderson @ 2015-08-24 16:43 UTC (permalink / raw)
To: Peter Maydell; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 08/24/2015 09:29 AM, Peter Maydell wrote:
>> - LWNA_ADD_IMM8_OPCODE_X1 = 21,
>> + LDNA_ADD_IMM8_OPCODE_X1 = 21,
>> MFSPR_IMM8_OPCODE_X1 = 22,
>> MF_UNARY_OPCODE_X1 = 31,
>> MM_BF_OPCODE_X0 = 7,
>> --
>> 2.4.3
>
> Should we feed this fix and the one in patch 6 back to
> the kernel?
Probably.
r~
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions
[not found] ` <55DB96D7.9000105@hotmail.com>
@ 2015-08-24 22:12 ` Chen Gang
[not found] ` <55E1B1AF.3040407@hotmail.com>
0 siblings, 1 reply; 80+ messages in thread
From: Chen Gang @ 2015-08-24 22:12 UTC (permalink / raw)
To: rth, qemu-devel; +Cc: walt, Chris Metcalf, Peter Maydell
On 8/25/15 00:17, Richard Henderson wrote:
> I've flushed out the v13 I posted last Thursday to handle all the
> instructions required to execute Hello World. In the process I
> found a number of bugs and design flaws in v13, and reshaped the
> translation a bit to better handle insns with no register outputs.
>
OK, thank you for your work (originally, I really did not kown that it
would generate so many patches -- almost 3 times that I supposed).
> Please review.
>
> After this, I would hope that Chen Gang will follow up to implement
> the rest of the instructions that he has identified running the
> gcc testsuite, and then start in on the floating point.
>
OK, thanks, I shall continue based on it, after it is integrated into
qemu master (after Reviewed-by another members).
During the next 2-4 days I shall try to fix one gcc bugzilla issue, then
turn back to qemu, hope I can succeed. (during these passed days, I sent
3 paches to kernel, and 2 of them are applied, one is waiting review).
Thanks.
>
> r~
>
>
> Chen Gang (9):
> linux-user: tilegx: Firstly add architecture related features
> linux-user: Support tilegx architecture in linux-user
> linux-user: Conditionalize syscalls which are not defined in tilegx
> target-tilegx: Add opcode basic implementation from Tilera Corporation
> target-tilegx: Modify opcode_tilegx.h to fit QEMU usage
> target-tilegx: Add special register information from Tilera
> Corporation
> target-tilegx: Add cpu basic features for linux-user
> target-tilegx: Add several helpers for instructions translation
> target-tilegx: Add TILE-Gx building files
>
> Richard Henderson (24):
> target-tilegx: Modify _SPECIAL_ opcodes
> target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1
> target-tilegx: Framework for decoding bundles
> target-tilegx: Generate SEGV properly
> target-tilegx: Handle simple logical operations
> target-tilegx: Handle arithmetic instructions
> target-tilegx: Handle most bit manipulation instructions
> target-tilegx: Handle basic load and store instructions
> target-tilegx: Handle post-increment load and store instructions
> target-tilegx: Handle unconditional jump instructions
> target-tilegx: Handle conditional branch instructions
> target-tilegx: Handle comparison instructions
> target-tilegx: Implement system and memory management instructions
> target-tilegx: Handle bitfield instructions
> target-tilegx: Handle shift instructions
> target-tilegx: Handle conditional move instructions
> target-tilegx: Handle scalar multiply instructions
> target-tilegx: Handle mask instructions
> target-tilegx: Handle v1cmpeq, v1cmpne
> target-tilegx: Handle mtspr, mfspr
> target-tilegx: Handle atomic instructions
> target-tilegx: Handle v4int_l/h
> target-tilegx: Handle v1shli, v1shrui
> target-tilegx: Handle v1shl, v1shru, v1shrs
>
> configure | 2 +
> default-configs/tilegx-linux-user.mak | 1 +
> include/elf.h | 2 +
> linux-user/elfload.c | 23 +
> linux-user/main.c | 298 +++++
> linux-user/syscall.c | 50 +-
> linux-user/syscall_defs.h | 14 +-
> linux-user/tilegx/syscall.h | 40 +
> linux-user/tilegx/syscall_nr.h | 324 +++++
> linux-user/tilegx/target_cpu.h | 35 +
> linux-user/tilegx/target_signal.h | 28 +
> linux-user/tilegx/target_structs.h | 46 +
> linux-user/tilegx/termbits.h | 274 +++++
> target-tilegx/Makefile.objs | 1 +
> target-tilegx/cpu.c | 173 +++
> target-tilegx/cpu.h | 177 +++
> target-tilegx/helper.c | 93 ++
> target-tilegx/helper.h | 10 +
> target-tilegx/opcode_tilegx.h | 1406 ++++++++++++++++++++++
> target-tilegx/simd_helper.c | 63 +
> target-tilegx/spr_def_64.h | 216 ++++
> target-tilegx/translate.c | 2135 +++++++++++++++++++++++++++++++++
> 22 files changed, 5405 insertions(+), 6 deletions(-)
> create mode 100644 default-configs/tilegx-linux-user.mak
> create mode 100644 linux-user/tilegx/syscall.h
> create mode 100644 linux-user/tilegx/syscall_nr.h
> create mode 100644 linux-user/tilegx/target_cpu.h
> create mode 100644 linux-user/tilegx/target_signal.h
> create mode 100644 linux-user/tilegx/target_structs.h
> create mode 100644 linux-user/tilegx/termbits.h
> create mode 100644 target-tilegx/Makefile.objs
> create mode 100644 target-tilegx/cpu.c
> create mode 100644 target-tilegx/cpu.h
> create mode 100644 target-tilegx/helper.c
> create mode 100644 target-tilegx/helper.h
> create mode 100644 target-tilegx/opcode_tilegx.h
> create mode 100644 target-tilegx/simd_helper.c
> create mode 100644 target-tilegx/spr_def_64.h
> create mode 100644 target-tilegx/translate.c
>
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions Richard Henderson
@ 2015-08-25 4:15 ` Richard Henderson
[not found] ` <55DC69B0.1040000@hotmail.com>
0 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-25 4:15 UTC (permalink / raw)
To: qemu-devel; +Cc: walt, cmetcalf, xili_gchen_5257, peter.maydell
On 08/24/2015 09:17 AM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index 210e912..2a0798a 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -180,6 +180,19 @@ static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
> tcg_temp_free(t0);
> }
>
> +static void gen_atomic_excp(DisasContext *dc, unsigned dest, unsigned srca,
> + unsigned srcb, TileExcp excp)
> +{
> +#ifdef CONFIG_USER_ONLY
> + TCGv_i32 t = tcg_const_i32((dest << 16) | (srca << 8) | srcb);
> + tcg_gen_st_i32(t, cpu_env, offsetof(CPUTLGState, excparam));
> + tcg_temp_free_i32(t);
> + gen_exception(dc, excp);
> +#else
> + gen_exception(dc, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
> +#endif
> +}
This is broken. While it does work well enough for Hello World, implementing a
non-trap instruction with an exception is extremely dicey for TileGX. The
issue is that TileGX bundles operate atomically, with no RAW issues between the
instructions of the bundle.
Consider a bundle like
{ add r0, r0, r1 ; exch r2, r0, r3 }
In Chen's implementation, the writeback to r0 would occur before the exception,
and so the exch would happen to the wrong address. In my implementation here,
the exception would occur before the writeback, and so the result of the add
would be discarded.
While retaining the current start_exclusive scheme, it would appear that we
need to store more data here -- to wit, the contents of the registers not their
numbers -- and delay the exception until after writeback.
Even better, of course, would be to not exit the TB at all, and use host atomic
instructions... I suppose that multi-threading patch set is still in limbo?
r~
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions
[not found] ` <55DC69B0.1040000@hotmail.com>
@ 2015-08-25 13:11 ` Chen Gang
2015-08-25 13:12 ` Chen Gang
0 siblings, 1 reply; 80+ messages in thread
From: Chen Gang @ 2015-08-25 13:11 UTC (permalink / raw)
To: rth, qemu-devel; +Cc: walt, Chris Metcalf, Peter Maydell
On 8/25/15 12:15, Richard Henderson wrote:
> On 08/24/2015 09:17 AM, Richard Henderson wrote:
>> Signed-off-by: Richard Henderson <rth@twiddle.net>
>> ---
>> target-tilegx/translate.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 49 insertions(+), 1 deletion(-)
>>
>> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
>> index 210e912..2a0798a 100644
>> --- a/target-tilegx/translate.c
>> +++ b/target-tilegx/translate.c
>> @@ -180,6 +180,19 @@ static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
>> tcg_temp_free(t0);
>> }
>>
>> +static void gen_atomic_excp(DisasContext *dc, unsigned dest, unsigned srca,
>> + unsigned srcb, TileExcp excp)
>> +{
>> +#ifdef CONFIG_USER_ONLY
>> + TCGv_i32 t = tcg_const_i32((dest << 16) | (srca << 8) | srcb);
>> + tcg_gen_st_i32(t, cpu_env, offsetof(CPUTLGState, excparam));
>> + tcg_temp_free_i32(t);
>> + gen_exception(dc, excp);
>> +#else
>> + gen_exception(dc, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
>> +#endif
>> +}
Originally, I used set_exception(), not gen_exception().
>
>
> This is broken. While it does work well enough for Hello World, implementing a non-trap instruction with an exception is extremely dicey for TileGX. The issue is that TileGX bundles operate atomically, with no RAW issues between the instructions of the bundle.
>
> Consider a bundle like
>
> { add r0, r0, r1 ; exch r2, r0, r3 }
>
> In Chen's implementation, the writeback to r0 would occur before the exception, and so the exch would happen to the wrong address. In my implementation here, the exception would occur before the writeback, and so the result of the add would be discarded.
We use tmp regs for buffering the r0.
- calculate x1 pipe, and save result to r0 tmp reg.
- exch the original r0 and r3 to r2 tmp reg.
- set exception flag (which will cause exception, later).
- save the result tmp regs to r0 or r2.
- gen exception.
>
> While retaining the current start_exclusive scheme, it would appear that we need to store more data here -- to wit, the contents of the registers not their numbers -- and delay the exception until after writeback.
>
> Even better, of course, would be to not exit the TB at all, and use host atomic instructions... I suppose that multi-threading patch set is still in limbo?
>
I guess, we need not.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions
2015-08-25 13:11 ` Chen Gang
@ 2015-08-25 13:12 ` Chen Gang
2015-08-25 14:28 ` Richard Henderson
0 siblings, 1 reply; 80+ messages in thread
From: Chen Gang @ 2015-08-25 13:12 UTC (permalink / raw)
To: rth, qemu-devel; +Cc: walt, Chris Metcalf, Peter Maydell
----------------------------------------
> From: xili_gchen_5257@hotmail.com
> To: rth@twiddle.net; qemu-devel@nongnu.org
> CC: walt@tilera.com; cmetcalf@ezchip.com; peter.maydell@linaro.org
> Subject: Re: [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions
> Date: Tue, 25 Aug 2015 21:11:11 +0800
>
> On 8/25/15 12:15, Richard Henderson wrote:
>> On 08/24/2015 09:17 AM, Richard Henderson wrote:
>>> Signed-off-by: Richard Henderson <rth@twiddle.net>
>>> ---
>>> target-tilegx/translate.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++-
>>> 1 file changed, 49 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
>>> index 210e912..2a0798a 100644
>>> --- a/target-tilegx/translate.c
>>> +++ b/target-tilegx/translate.c
>>> @@ -180,6 +180,19 @@ static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
>>> tcg_temp_free(t0);
>>> }
>>>
>>> +static void gen_atomic_excp(DisasContext *dc, unsigned dest, unsigned srca,
>>> + unsigned srcb, TileExcp excp)
>>> +{
>>> +#ifdef CONFIG_USER_ONLY
>>> + TCGv_i32 t = tcg_const_i32((dest << 16) | (srca << 8) | srcb);
>>> + tcg_gen_st_i32(t, cpu_env, offsetof(CPUTLGState, excparam));
>>> + tcg_temp_free_i32(t);
>>> + gen_exception(dc, excp);
>>> +#else
>>> + gen_exception(dc, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
>>> +#endif
>>> +}
>
> Originally, I used set_exception(), not gen_exception().
>
>>
>>
>> This is broken. While it does work well enough for Hello World, implementing a non-trap instruction with an exception is extremely dicey for TileGX. The issue is that TileGX bundles operate atomically, with no RAW issues between the instructions of the bundle.
>>
>> Consider a bundle like
>>
>> { add r0, r0, r1 ; exch r2, r0, r3 }
>>
>> In Chen's implementation, the writeback to r0 would occur before the exception, and so the exch would happen to the wrong address. In my implementation here, the exception would occur before the writeback, and so the result of the add would be discarded.
>
> We use tmp regs for buffering the r0.
>
> - calculate x1 pipe, and save result to r0 tmp reg.
>
Oh, typo, calculate x0 pipe, and save result to r0 tmp reg.
> - exch the original r0 and r3 to r2 tmp reg.
>
> - set exception flag (which will cause exception, later).
>
> - save the result tmp regs to r0 or r2.
>
> - gen exception.
>
>>
>> While retaining the current start_exclusive scheme, it would appear that we need to store more data here -- to wit, the contents of the registers not their numbers -- and delay the exception until after writeback.
>>
>> Even better, of course, would be to not exit the TB at all, and use host atomic instructions... I suppose that multi-threading patch set is still in limbo?
>>
>
> I guess, we need not.
>
>
> Thanks.
> --
> Chen Gang
>
> Open, share, and attitude like air, water, and life which God blessed
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions
2015-08-25 13:12 ` Chen Gang
@ 2015-08-25 14:28 ` Richard Henderson
[not found] ` <55DCE21F.9000103@hotmail.com>
0 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-08-25 14:28 UTC (permalink / raw)
To: Chen Gang, qemu-devel; +Cc: walt, Chris Metcalf, Peter Maydell
On 08/25/2015 06:12 AM, Chen Gang wrote:
>
>
> ----------------------------------------
>> From: xili_gchen_5257@hotmail.com
>> To: rth@twiddle.net; qemu-devel@nongnu.org
>> CC: walt@tilera.com; cmetcalf@ezchip.com; peter.maydell@linaro.org
>> Subject: Re: [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions
>> Date: Tue, 25 Aug 2015 21:11:11 +0800
>>
>> On 8/25/15 12:15, Richard Henderson wrote:
>>> On 08/24/2015 09:17 AM, Richard Henderson wrote:
>>>> Signed-off-by: Richard Henderson <rth@twiddle.net>
>>>> ---
>>>> target-tilegx/translate.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++-
>>>> 1 file changed, 49 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
>>>> index 210e912..2a0798a 100644
>>>> --- a/target-tilegx/translate.c
>>>> +++ b/target-tilegx/translate.c
>>>> @@ -180,6 +180,19 @@ static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
>>>> tcg_temp_free(t0);
>>>> }
>>>>
>>>> +static void gen_atomic_excp(DisasContext *dc, unsigned dest, unsigned srca,
>>>> + unsigned srcb, TileExcp excp)
>>>> +{
>>>> +#ifdef CONFIG_USER_ONLY
>>>> + TCGv_i32 t = tcg_const_i32((dest << 16) | (srca << 8) | srcb);
>>>> + tcg_gen_st_i32(t, cpu_env, offsetof(CPUTLGState, excparam));
>>>> + tcg_temp_free_i32(t);
>>>> + gen_exception(dc, excp);
>>>> +#else
>>>> + gen_exception(dc, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
>>>> +#endif
>>>> +}
>>
>> Originally, I used set_exception(), not gen_exception().
>>
>>>
>>>
>>> This is broken. While it does work well enough for Hello World, implementing a non-trap instruction with an exception is extremely dicey for TileGX. The issue is that TileGX bundles operate atomically, with no RAW issues between the instructions of the bundle.
>>>
>>> Consider a bundle like
>>>
>>> { add r0, r0, r1 ; exch r2, r0, r3 }
>>>
>>> In Chen's implementation, the writeback to r0 would occur before the exception, and so the exch would happen to the wrong address. In my implementation here, the exception would occur before the writeback, and so the result of the add would be discarded.
>>
>> We use tmp regs for buffering the r0.
>>
>> - calculate x1 pipe, and save result to r0 tmp reg.
>>
>
> Oh, typo, calculate x0 pipe, and save result to r0 tmp reg.
>
>> - exch the original r0 and r3 to r2 tmp reg.
>>
>> - set exception flag (which will cause exception, later).
>>
>> - save the result tmp regs to r0 or r2.
>>
>> - gen exception.
Exactly. Now re-read what I wrote and see if you can spot the problem with this.
r~
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions
[not found] ` <55DCE21F.9000103@hotmail.com>
@ 2015-08-25 21:45 ` Chen Gang
0 siblings, 0 replies; 80+ messages in thread
From: Chen Gang @ 2015-08-25 21:45 UTC (permalink / raw)
To: rth, qemu-devel; +Cc: walt, Chris Metcalf, Peter Maydell
On 8/25/15 22:28, Richard Henderson wrote:
> On 08/25/2015 06:12 AM, Chen Gang wrote:
>>>>
>>>> Consider a bundle like
>>>>
>>>> { add r0, r0, r1 ; exch r2, r0, r3 }
>>>>
>>>> In Chen's implementation, the writeback to r0 would occur before the exception, and so the exch would happen to the wrong address. In my implementation here, the exception would occur before the writeback, and so the result of the add would be discarded.
>>>
>>> We use tmp regs for buffering the r0.
>>>
>>> - calculate x1 pipe, and save result to r0 tmp reg.
>>>
>>
>> Oh, typo, calculate x0 pipe, and save result to r0 tmp reg.
>>
>>> - exch the original r0 and r3 to r2 tmp reg.
>>>
>>> - set exception flag (which will cause exception, later).
>>>
>>> - save the result tmp regs to r0 or r2.
>>>
>>> - gen exception.
>
> Exactly. Now re-read what I wrote and see if you can spot the problem with this.
>
OK, thanks. In my memory, originally, we discussed about related things,
you provided several good ideas (temp regs, and gen exceptions ...).
Based on them, I implemented it in this way, hope it is correct.
At present, for gcc testsuite, I met several (10+) pending issues, which
need to be fixed, next. So I guess, there must be still any issues which
we did not find in the current whole tilegx code.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 07/33] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 07/33] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 Richard Henderson
2015-08-24 16:29 ` Peter Maydell
@ 2015-08-26 17:11 ` Chris Metcalf
2015-08-29 14:30 ` Peter Maydell
2 siblings, 0 replies; 80+ messages in thread
From: Chris Metcalf @ 2015-08-26 17:11 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: walt, xili_gchen_5257, peter.maydell
I have queued both this and the 06/33 patch in the linux-tile tree as a
single patch for the kernel when the 4.3 merge window opens,
with Richard's Reported-By. Thanks!
Both of these appear to be cut-and-paste errors from the tilepro
versions of the files.
On 08/24/2015 12:17 PM, Richard Henderson wrote:
> An obvious typo in the mnemonic here.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/opcode_tilegx.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-tilegx/opcode_tilegx.h b/target-tilegx/opcode_tilegx.h
> index 3b8bf4f..989436d 100644
> --- a/target-tilegx/opcode_tilegx.h
> +++ b/target-tilegx/opcode_tilegx.h
> @@ -1015,7 +1015,7 @@ enum
> LD_UNARY_OPCODE_X1 = 29,
> LNK_UNARY_OPCODE_X1 = 30,
> LNK_UNARY_OPCODE_Y1 = 14,
> - LWNA_ADD_IMM8_OPCODE_X1 = 21,
> + LDNA_ADD_IMM8_OPCODE_X1 = 21,
> MFSPR_IMM8_OPCODE_X1 = 22,
> MF_UNARY_OPCODE_X1 = 31,
> MM_BF_OPCODE_X0 = 7,
--
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions
[not found] ` <55E1B1AF.3040407@hotmail.com>
@ 2015-08-29 13:19 ` Chen Gang
[not found] ` <55E2822E.4000805@hotmail.com>
0 siblings, 1 reply; 80+ messages in thread
From: Chen Gang @ 2015-08-29 13:19 UTC (permalink / raw)
To: rth, qemu-devel; +Cc: walt, Chris Metcalf, Peter Maydell
Is tilegx patches OK to qemu mater tree?
Or shall I do anything for it? If I should do something for it, please
let me know, I shall try.
I almost finished analyzing one gcc bug (found root cause, got correct
result with my patch), it was waiting review. If I needn't do anything
for tilegx merging, I shall continue to analyze tilegx gcc testsuite.
Thanks.
On 8/25/15 06:12, Chen Gang wrote:
>
> On 8/25/15 00:17, Richard Henderson wrote:
>> I've flushed out the v13 I posted last Thursday to handle all the
>> instructions required to execute Hello World. In the process I
>> found a number of bugs and design flaws in v13, and reshaped the
>> translation a bit to better handle insns with no register outputs.
>>
>
> OK, thank you for your work (originally, I really did not kown that it
> would generate so many patches -- almost 3 times that I supposed).
>
>
>> Please review.
>>
>> After this, I would hope that Chen Gang will follow up to implement
>> the rest of the instructions that he has identified running the
>> gcc testsuite, and then start in on the floating point.
>>
>
> OK, thanks, I shall continue based on it, after it is integrated into
> qemu master (after Reviewed-by another members).
>
> During the next 2-4 days I shall try to fix one gcc bugzilla issue, then
> turn back to qemu, hope I can succeed. (during these passed days, I sent
> 3 paches to kernel, and 2 of them are applied, one is waiting review).
>
>
> Thanks.
>
>>
>> r~
>>
>>
>> Chen Gang (9):
>> linux-user: tilegx: Firstly add architecture related features
>> linux-user: Support tilegx architecture in linux-user
>> linux-user: Conditionalize syscalls which are not defined in tilegx
>> target-tilegx: Add opcode basic implementation from Tilera Corporation
>> target-tilegx: Modify opcode_tilegx.h to fit QEMU usage
>> target-tilegx: Add special register information from Tilera
>> Corporation
>> target-tilegx: Add cpu basic features for linux-user
>> target-tilegx: Add several helpers for instructions translation
>> target-tilegx: Add TILE-Gx building files
>>
>> Richard Henderson (24):
>> target-tilegx: Modify _SPECIAL_ opcodes
>> target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1
>> target-tilegx: Framework for decoding bundles
>> target-tilegx: Generate SEGV properly
>> target-tilegx: Handle simple logical operations
>> target-tilegx: Handle arithmetic instructions
>> target-tilegx: Handle most bit manipulation instructions
>> target-tilegx: Handle basic load and store instructions
>> target-tilegx: Handle post-increment load and store instructions
>> target-tilegx: Handle unconditional jump instructions
>> target-tilegx: Handle conditional branch instructions
>> target-tilegx: Handle comparison instructions
>> target-tilegx: Implement system and memory management instructions
>> target-tilegx: Handle bitfield instructions
>> target-tilegx: Handle shift instructions
>> target-tilegx: Handle conditional move instructions
>> target-tilegx: Handle scalar multiply instructions
>> target-tilegx: Handle mask instructions
>> target-tilegx: Handle v1cmpeq, v1cmpne
>> target-tilegx: Handle mtspr, mfspr
>> target-tilegx: Handle atomic instructions
>> target-tilegx: Handle v4int_l/h
>> target-tilegx: Handle v1shli, v1shrui
>> target-tilegx: Handle v1shl, v1shru, v1shrs
>>
>> configure | 2 +
>> default-configs/tilegx-linux-user.mak | 1 +
>> include/elf.h | 2 +
>> linux-user/elfload.c | 23 +
>> linux-user/main.c | 298 +++++
>> linux-user/syscall.c | 50 +-
>> linux-user/syscall_defs.h | 14 +-
>> linux-user/tilegx/syscall.h | 40 +
>> linux-user/tilegx/syscall_nr.h | 324 +++++
>> linux-user/tilegx/target_cpu.h | 35 +
>> linux-user/tilegx/target_signal.h | 28 +
>> linux-user/tilegx/target_structs.h | 46 +
>> linux-user/tilegx/termbits.h | 274 +++++
>> target-tilegx/Makefile.objs | 1 +
>> target-tilegx/cpu.c | 173 +++
>> target-tilegx/cpu.h | 177 +++
>> target-tilegx/helper.c | 93 ++
>> target-tilegx/helper.h | 10 +
>> target-tilegx/opcode_tilegx.h | 1406 ++++++++++++++++++++++
>> target-tilegx/simd_helper.c | 63 +
>> target-tilegx/spr_def_64.h | 216 ++++
>> target-tilegx/translate.c | 2135 +++++++++++++++++++++++++++++++++
>> 22 files changed, 5405 insertions(+), 6 deletions(-)
>> create mode 100644 default-configs/tilegx-linux-user.mak
>> create mode 100644 linux-user/tilegx/syscall.h
>> create mode 100644 linux-user/tilegx/syscall_nr.h
>> create mode 100644 linux-user/tilegx/target_cpu.h
>> create mode 100644 linux-user/tilegx/target_signal.h
>> create mode 100644 linux-user/tilegx/target_structs.h
>> create mode 100644 linux-user/tilegx/termbits.h
>> create mode 100644 target-tilegx/Makefile.objs
>> create mode 100644 target-tilegx/cpu.c
>> create mode 100644 target-tilegx/cpu.h
>> create mode 100644 target-tilegx/helper.c
>> create mode 100644 target-tilegx/helper.h
>> create mode 100644 target-tilegx/opcode_tilegx.h
>> create mode 100644 target-tilegx/simd_helper.c
>> create mode 100644 target-tilegx/spr_def_64.h
>> create mode 100644 target-tilegx/translate.c
>>
>
> --
> Chen Gang
>
> Open, share, and attitude like air, water, and life which God blessed
>
>
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 06/33] target-tilegx: Modify _SPECIAL_ opcodes
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 06/33] target-tilegx: Modify _SPECIAL_ opcodes Richard Henderson
@ 2015-08-29 14:29 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-08-29 14:29 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Both ADDX_SPECIAL_0_OPCODE_Y1 and ADD_SPECIAL_0_OPCODE_Y1
> do not appear to be "special" in any way, except that they
> don't follow the normal naming convention using _RRR_.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/opcode_tilegx.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 07/33] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 07/33] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 Richard Henderson
2015-08-24 16:29 ` Peter Maydell
2015-08-26 17:11 ` Chris Metcalf
@ 2015-08-29 14:30 ` Peter Maydell
2 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-08-29 14:30 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> An obvious typo in the mnemonic here.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/opcode_tilegx.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 10/33] target-tilegx: Add several helpers for instructions translation
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 10/33] target-tilegx: Add several helpers for instructions translation Richard Henderson
@ 2015-08-29 14:37 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-08-29 14:37 UTC (permalink / raw)
To: Richard Henderson
Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> From: Chen Gang <xili_gchen_5257@hotmail.com>
>
> The related instructions are exception, cntlz, cnttz, shufflebytes.
>
> Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com>
> Message-Id: <BLU436-SMTP83F96FD8422BE49AFDC9DFB9660@phx.gbl>
> [rth: Remove incorrect implementation of add_saturate.]
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> +/*
> + * Functional Description
> + * uint64_t a = rf[SrcA];
> + * uint64_t b = rf[SrcB];
> + * uint64_t d = rf[Dest];
> + * uint64_t output = 0;
> + * unsigned int counter;
> + * for (counter = 0; counter < (WORD_SIZE / BYTE_SIZE); counter++)
> + * {
> + * int sel = getByte (b, counter) & 0xf;
> + * uint8_t byte = (sel < 8) ? getByte (d, sel) : getByte (a, (sel - 8));
> + * output = setByte (output, counter, byte);
> + * }
> + * rf[Dest] = output;
> + */
> +uint64_t helper_shufflebytes(uint64_t dest, uint64_t srca, uint64_t srcb)
> +{
> + uint64_t vdst = 0;
> + int count;
> +
> + for (count = 0; count < 64; count += 8) {
> + uint64_t sel = srcb >> count;
> + uint64_t src = (sel & 8) ? srca : dest;
> + vdst |= ((src >> ((sel & 7) * 8)) & 0xff) << count;
I would have used extract64(src, (sel & 7) * 8, 8)
as being slightly easier to read in comparison with the quoted
pseudocode, but it's not a big deal, so
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 11/33] target-tilegx: Framework for decoding bundles
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 11/33] target-tilegx: Framework for decoding bundles Richard Henderson
@ 2015-08-29 14:50 ` Peter Maydell
[not found] ` <55E24808.5000302@hotmail.com>
2015-08-29 21:08 ` Peter Maydell
1 sibling, 1 reply; 80+ messages in thread
From: Peter Maydell @ 2015-08-29 14:50 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 1145 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 1145 insertions(+)
> create mode 100644 target-tilegx/translate.c
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> new file mode 100644
> index 0000000..a2d597d
> --- /dev/null
> +++ b/target-tilegx/translate.c
> @@ -0,0 +1,1145 @@
> +/*
> + * QEMU TILE-Gx CPU
> + *
> + * Copyright (c) 2015 Chen Gang
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see
> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
> + */
> +
> +#include "cpu.h"
> +#include "qemu/log.h"
> +#include "disas/disas.h"
> +#include "tcg-op.h"
> +#include "exec/cpu_ldst.h"
> +#include "opcode_tilegx.h"
> +
> +#define FMT64X "%016" PRIx64
> +
> +static TCGv_ptr cpu_env;
> +static TCGv cpu_pc;
> +static TCGv cpu_regs[TILEGX_R_COUNT];
> +
> +static const char * const reg_names[64] = {
> + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
> + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
> + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
> + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
> + "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
> + "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
> + "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr",
> + "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn2", "zero"
> +};
> +
> +/* Modified registers are cached in temporaries until the end of the bundle. */
> +typedef struct {
> + unsigned reg;
> + TCGv val;
> +} DisasContextTemp;
> +
> +#define MAX_WRITEBACK 4
> +
> +/* This is the state at translation time. */
> +typedef struct {
> + uint64_t pc; /* Current pc */
> +
> + TCGv zero; /* For zero register */
> +
> + DisasContextTemp wb[MAX_WRITEBACK];
> + int num_wb;
> + int mmuidx;
> + bool exit_tb;
> +
> + struct {
> + TCGCond cond; /* branch condition */
> + TCGv dest; /* branch destination */
> + TCGv val1; /* value to be compared against zero, for cond */
> + } jmp; /* Jump object, only once in each TB block */
> +} DisasContext;
> +
> +#include "exec/gen-icount.h"
> +
> +/* Differentiate the various pipe encodings. */
> +#define TY_X0 0
> +#define TY_X1 1
> +#define TY_Y0 2
> +#define TY_Y1 3
> +
> +/* Remerge the base opcode and extension fields for switching.
> + The X opcode fields are 3 bits; Y0/Y1 opcode fields are 4 bits;
> + Y2 opcode field is 2 bits. */
> +#define OE(OP, EXT, XY) (TY_##XY + OP * 4 + EXT * 64)
Slightly odd to assemble bitfields with multiplies and adds
rather than shifts and logical-or.
> + qemu_log_mask(CPU_LOG_TB_IN_ASM, " %" PRIx64 ": { ", dc->pc);
> + if (get_Mode(bundle)) {
> + notice_excp(dc, bundle, "y0", decode_y0(dc, bundle));
> + qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
> + notice_excp(dc, bundle, "y1", decode_y1(dc, bundle));
> + qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
> + notice_excp(dc, bundle, "y2", decode_y2(dc, bundle));
> + } else {
> + notice_excp(dc, bundle, "x0", decode_x0(dc, bundle));
> + qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
> + notice_excp(dc, bundle, "x1", decode_x1(dc, bundle));
> + }
I notice that even if the first insn in a bundle generates an
exception we'll go ahead and generate unreachable code for
the rest.
I haven't tried to find and compare against any instruction
set documentation, but structurally it looks good, so
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 12/33] target-tilegx: Generate SEGV properly
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 12/33] target-tilegx: Generate SEGV properly Richard Henderson
@ 2015-08-29 14:51 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-08-29 14:51 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> linux-user/main.c | 3 +++
> target-tilegx/cpu.c | 5 ++++-
> target-tilegx/cpu.h | 2 ++
> 3 files changed, 9 insertions(+), 1 deletion(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 14/33] target-tilegx: Handle simple logical operations
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 14/33] target-tilegx: Handle simple logical operations Richard Henderson
@ 2015-08-29 14:58 ` Peter Maydell
2015-09-01 2:10 ` Richard Henderson
0 siblings, 1 reply; 80+ messages in thread
From: Peter Maydell @ 2015-08-29 14:58 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 99 +++++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 96 insertions(+), 3 deletions(-)
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index a2d597d..066d351 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -106,9 +106,64 @@ static void gen_exception(DisasContext *dc, TileExcp num)
> dc->exit_tb = true;
> }
>
> +static bool check_gr(DisasContext *dc, uint8_t reg)
> +{
> + if (likely(reg < TILEGX_R_COUNT)) {
> + return true;
> + }
> +
> + switch (reg) {
> + case TILEGX_R_SN:
> + case TILEGX_R_ZERO:
> + break;
> + case TILEGX_R_IDN0:
> + case TILEGX_R_IDN1:
> + gen_exception(dc, TILEGX_EXCP_REG_IDN_ACCESS);
> + break;
> + case TILEGX_R_UDN0:
> + case TILEGX_R_UDN1:
> + case TILEGX_R_UDN2:
> + case TILEGX_R_UDN3:
> + gen_exception(dc, TILEGX_EXCP_REG_UDN_ACCESS);
Why does this function generate an exception immediately
rather than returning a TILEGX_EXCP_* code the way the
decode framework seems to be set up to work?
> + break;
> + default:
> + g_assert_not_reached();
> + }
> + return false;
> +}
> +
> +static TCGv load_zero(DisasContext *dc)
> +{
> + if (TCGV_IS_UNUSED_I64(dc->zero)) {
> + dc->zero = tcg_const_i64(0);
> + }
> + return dc->zero;
> +}
The ARM frontend has made me a bit suspicious of TCGv
and target_long rather than specifically using TCGv_i32
or i64 and uint32_t/uint64_t, but I guess it makes sense
here.
Rest of the patch looks OK.
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 15/33] target-tilegx: Handle arithmetic instructions
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 15/33] target-tilegx: Handle arithmetic instructions Richard Henderson
@ 2015-08-29 15:03 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-08-29 15:03 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 95 ++++++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 89 insertions(+), 6 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 16/33] target-tilegx: Handle most bit manipulation instructions
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 16/33] target-tilegx: Handle most bit manipulation instructions Richard Henderson
@ 2015-08-29 15:26 ` Peter Maydell
2015-09-01 2:26 ` Richard Henderson
0 siblings, 1 reply; 80+ messages in thread
From: Peter Maydell @ 2015-08-29 15:26 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Omitting crc instructions.
I'm not a fan of commit message bodies that rely on reading
the subject line to make sense (partly because my mail
client doesn't put the subject line very prominently
when reading the email...)
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/helper.c | 23 ++++++++++++++++++
> target-tilegx/helper.h | 2 ++
> target-tilegx/translate.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++-
> 3 files changed, 84 insertions(+), 1 deletion(-)
>
> diff --git a/target-tilegx/helper.c b/target-tilegx/helper.c
> index ea66da0..6aba681 100644
> --- a/target-tilegx/helper.c
> +++ b/target-tilegx/helper.c
> @@ -40,6 +40,29 @@ uint64_t helper_cnttz(uint64_t arg)
> return ctz64(arg);
> }
>
> +uint64_t helper_pcnt(uint64_t arg)
> +{
> + return ctpop64(arg);
> +}
> +
> +uint64_t helper_revbits(uint64_t arg)
> +{
> + /* Assign the correct byte position. */
> + arg = bswap64(arg);
> +
> + /* Assign the correct nibble position. */
> + arg = ((arg & 0xf0f0f0f0f0f0f0f0ULL) >> 4)
> + | ((arg & 0x0f0f0f0f0f0f0f0fULL) << 4);
> +
> + /* Assign the correct bit position. */
> + arg = ((arg & 0x8888888888888888ULL) >> 3)
> + | ((arg & 0x4444444444444444ULL) >> 1)
> + | ((arg & 0x2222222222222222ULL) << 1)
> + | ((arg & 0x1111111111111111ULL) << 3);
> +
> + return arg;
> +}
AArch64 has this exact same operation; maybe we should
factor it out into bitops.h ?
> +
> /*
> * Functional Description
> * uint64_t a = rf[SrcA];
> diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
> index fd5517e..644d313 100644
> --- a/target-tilegx/helper.h
> +++ b/target-tilegx/helper.h
> @@ -1,4 +1,6 @@
> DEF_HELPER_2(exception, noreturn, env, i32)
> DEF_HELPER_FLAGS_1(cntlz, TCG_CALL_NO_RWG_SE, i64, i64)
> DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
> +DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64)
> +DEF_HELPER_FLAGS_1(revbits, TCG_CALL_NO_RWG_SE, i64, i64)
> DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index 090c006..82a34e5 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -177,6 +177,35 @@ static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
> tcg_temp_free(t0);
> }
>
> +static void gen_dblaligni(TCGv tdest, TCGv tsrca, TCGv tsrcb, int shr)
> +{
> + TCGv t0 = tcg_temp_new();
> +
> + tcg_gen_shri_tl(t0, tsrcb, shr);
> + tcg_gen_shli_tl(tdest, tsrca, 64 - shr);
> + tcg_gen_or_tl(tdest, tdest, t0);
> +
> + tcg_temp_free(t0);
> +}
> +
> +static void gen_dblalign(TCGv tdest, TCGv tsrcd, TCGv tsrca, TCGv tsrcb)
> +{
> + TCGv t0 = tcg_temp_new();
This operation seems sufficiently obscure that I think it would be
helpful to have a comment that explains what it is:
/* Shift the 128 bit value tsrca:tsrcd right by the number
* of bytes specified by the bottom 3 bits of tsrcb, and
* set tdest to the low 64 bits of the resulting value.
*/
(I think I've read the ISA correctly...)
Incidentally I deduce that we're not planning to support bigendian
mode?
> +
> + tcg_gen_andi_tl(t0, tsrcb, 7);
> + tcg_gen_shli_tl(t0, t0, 3);
> + tcg_gen_shr_tl(tdest, tsrcd, t0);
> +
> + /* Rather than creating and invalid shift, 64 - 0, perform the
> + left shift in two steps via the one's compliment. */
typos: "an", "complement".
It might be helpful to say what the maths going on here is
more explicitly:
We want to do "t0 = tsrca << (64 - t0)".
Twos' complement arithmetic on a 6-bit field tells us
that 64 - t0 == (t0 ^ 63) + 1. So we can do the shift in
two parts, neither of which will be 64 (since t0 can't be
63 here).
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 17/33] target-tilegx: Handle basic load and store instructions
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 17/33] target-tilegx: Handle basic load and store instructions Richard Henderson
@ 2015-08-29 20:45 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-08-29 20:45 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 131 ++++++++++++++++++++++++++++++++++++++++------
> 1 file changed, 116 insertions(+), 15 deletions(-)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 18/33] target-tilegx: Handle post-increment load and store instructions
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 18/33] target-tilegx: Handle post-increment " Richard Henderson
@ 2015-08-29 20:52 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-08-29 20:52 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 96 ++++++++++++++++++++++++++++++++++++++++++-----
> 1 file changed, 87 insertions(+), 9 deletions(-)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 19/33] target-tilegx: Handle unconditional jump instructions
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 19/33] target-tilegx: Handle unconditional jump instructions Richard Henderson
@ 2015-08-29 21:00 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-08-29 21:00 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 58 +++++++++++++++++++++++++++++++++--------------
> 1 file changed, 41 insertions(+), 17 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 11/33] target-tilegx: Framework for decoding bundles
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 11/33] target-tilegx: Framework for decoding bundles Richard Henderson
2015-08-29 14:50 ` Peter Maydell
@ 2015-08-29 21:08 ` Peter Maydell
2015-09-01 1:58 ` Richard Henderson
1 sibling, 1 reply; 80+ messages in thread
From: Peter Maydell @ 2015-08-29 21:08 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> + if (dc->jmp.cond != TCG_COND_NEVER) {
> + if (dc->jmp.cond == TCG_COND_ALWAYS) {
> + tcg_gen_mov_i64(cpu_pc, dc->jmp.dest);
> + } else {
> + TCGv next = tcg_const_i64(dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
> + tcg_gen_movcond_i64(dc->jmp.cond, cpu_pc,
> + dc->jmp.val1, load_zero(dc),
> + dc->jmp.dest, next);
> + tcg_temp_free_i64(dc->jmp.val1);
> + tcg_temp_free_i64(next);
> + }
> + tcg_temp_free_i64(dc->jmp.dest);
> + tcg_gen_exit_tb(0);
> + dc->exit_tb = true;
> + }
Doing conditional branches with movcond to pc means we'll
never be able to link TBs which end with conditional branches,
right?
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 20/33] target-tilegx: Handle conditional branch instructions
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 20/33] target-tilegx: Handle conditional branch instructions Richard Henderson
@ 2015-08-29 21:08 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-08-29 21:08 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 51 +++++++++++++++++++++++++++++++++++------------
> 1 file changed, 38 insertions(+), 13 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 21/33] target-tilegx: Handle comparison instructions
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 21/33] target-tilegx: Handle comparison instructions Richard Henderson
@ 2015-08-29 21:12 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-08-29 21:12 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 39 +++++++++++++++++++++++++++++++++------
> 1 file changed, 33 insertions(+), 6 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 22/33] target-tilegx: Implement system and memory management instructions
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 22/33] target-tilegx: Implement system and memory management instructions Richard Henderson
@ 2015-08-29 21:21 ` Peter Maydell
2015-09-01 5:16 ` Richard Henderson
0 siblings, 1 reply; 80+ messages in thread
From: Peter Maydell @ 2015-08-29 21:21 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Most of which are either nops or exceptions.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 94 ++++++++++++++++++++++++++++++++++-------------
> 1 file changed, 68 insertions(+), 26 deletions(-)
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index ea68902..5bdc8be 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -241,27 +241,82 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
> TCGv tdest, tsrca;
> const char *mnemonic;
> TCGMemOp memop;
> + TileExcp ret = TILEGX_EXCP_NONE;
>
> - /* Eliminate nops and jumps before doing anything else. */
> + /* Eliminate instructions with no output before doing anything else. */
> switch (opext) {
> case OE_RR_Y0(NOP):
> case OE_RR_Y1(NOP):
> case OE_RR_X0(NOP):
> case OE_RR_X1(NOP):
> mnemonic = "nop";
> - goto do_nop;
> + goto done0;
> case OE_RR_Y0(FNOP):
> case OE_RR_Y1(FNOP):
> case OE_RR_X0(FNOP):
> case OE_RR_X1(FNOP):
> mnemonic = "fnop";
> - do_nop:
> - if (srca || dest) {
> - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> + goto done0;
> + case OE_RR_X1(DRAIN):
> + mnemonic = "drain";
> + goto done0;
> + case OE_RR_X1(FLUSHWB):
> + mnemonic = "flushwb";
> + goto done0;
> + case OE_RR_X1(ILL):
> + case OE_RR_Y1(ILL):
> + ret = TILEGX_EXCP_OPCODE_UNKNOWN;
> + mnemonic = (dest == 0x1c && srca == 0x25 ? "bpt" : "ill");
> + goto done0;
> + case OE_RR_X1(MF):
> + mnemonic = "mf";
> + goto done0;
> + case OE_RR_X1(NAP):
> + /* ??? This should yield, especially in system mode. */
> + mnemonic = "nap";
> + goto done0;
> + case OE_RR_X1(SWINT0):
> + ret = TILEGX_EXCP_OPCODE_UNKNOWN;
> + mnemonic = "swint0";
> + goto done0;
> + case OE_RR_X1(SWINT1):
> + ret = TILEGX_EXCP_SYSCALL;
> + mnemonic = "swint1";
> + goto done0;
> + case OE_RR_X1(SWINT2):
> + ret = TILEGX_EXCP_OPCODE_UNKNOWN;
> + mnemonic = "swint2";
> + goto done0;
> + case OE_RR_X1(SWINT3):
> + ret = TILEGX_EXCP_OPCODE_UNKNOWN;
> + mnemonic = "swint3";
> + goto done0;
> + done0:
goto to immediately following label ?
> + if ((srca || dest) && ret == TILEGX_EXCP_NONE) {
> + ret = TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> }
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
> - return TILEGX_EXCP_NONE;
> + return ret;
>
> + case OE_RR_X1(DTLBPR):
> + ret = TILEGX_EXCP_OPCODE_UNKNOWN;
> + mnemonic = "dtlbpr";
> + goto done1;
> + case OE_RR_X1(FINV):
> + mnemonic = "finv";
> + goto done1;
> + case OE_RR_X1(FLUSH):
> + mnemonic = "flush";
> + goto done1;
> + case OE_RR_X1(ICOH):
> + mnemonic = "icoh";
> + goto done1;
> + case OE_RR_X1(INV):
> + mnemonic = "inv";
> + goto done1;
> + case OE_RR_X1(WH64):
> + mnemonic = "wh64";
> + goto done1;
> case OE_RR_X1(JRP):
> case OE_RR_Y1(JRP):
> mnemonic = "jrp";
> @@ -284,8 +339,12 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
> dc->jmp.cond = TCG_COND_ALWAYS;
> dc->jmp.dest = tcg_temp_new();
> tcg_gen_andi_tl(dc->jmp.dest, load_gr(dc, srca), ~7);
Should this really fall through into the added check ?
> + done1:
> + if (dest && ret == TILEGX_EXCP_NONE) {
> + ret = TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> + }
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);
> - return TILEGX_EXCP_NONE;
> + return ret;
> }
>
> tdest = dest_gr(dc, dest);
> @@ -302,17 +361,8 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
> gen_helper_cnttz(tdest, tsrca);
> mnemonic = "cnttz";
> break;
> - case OE_RR_X1(DRAIN):
> - case OE_RR_X1(DTLBPR):
> - case OE_RR_X1(FINV):
> - case OE_RR_X1(FLUSHWB):
> - case OE_RR_X1(FLUSH):
> case OE_RR_X0(FSINGLE_PACK1):
> case OE_RR_Y0(FSINGLE_PACK1):
> - case OE_RR_X1(ICOH):
> - case OE_RR_X1(ILL):
> - case OE_RR_Y1(ILL):
> - case OE_RR_X1(INV):
> case OE_RR_X1(IRET):
> return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> case OE_RR_X1(LD1S):
> @@ -381,14 +431,11 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
> case OE_RR_X1(LNK):
> case OE_RR_Y1(LNK):
> if (srca) {
> - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> + ret = TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
This code change seems unrelated to the rest of the patch?
Also we'll end up printing the disassembly as "lnk" rather
than whatever we should print for undefined instructions.
> }
> tcg_gen_movi_tl(tdest, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
> mnemonic = "lnk";
> break;
> - case OE_RR_X1(MF):
> - case OE_RR_X1(NAP):
> - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> case OE_RR_X0(PCNT):
> case OE_RR_Y0(PCNT):
> gen_helper_pcnt(tdest, tsrca);
> @@ -404,10 +451,6 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
> tcg_gen_bswap64_tl(tdest, tsrca);
> mnemonic = "revbytes";
> break;
> - case OE_RR_X1(SWINT0):
> - case OE_RR_X1(SWINT1):
> - case OE_RR_X1(SWINT2):
> - case OE_RR_X1(SWINT3):
> case OE_RR_X0(TBLIDXB0):
> case OE_RR_Y0(TBLIDXB0):
> case OE_RR_X0(TBLIDXB1):
> @@ -416,14 +459,13 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
> case OE_RR_Y0(TBLIDXB2):
> case OE_RR_X0(TBLIDXB3):
> case OE_RR_Y0(TBLIDXB3):
> - case OE_RR_X1(WH64):
> default:
> return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> }
>
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
> reg_names[dest], reg_names[srca]);
> - return TILEGX_EXCP_NONE;
> + return ret;
> }
>
> static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 11/33] target-tilegx: Framework for decoding bundles
[not found] ` <55E24808.5000302@hotmail.com>
@ 2015-08-30 0:01 ` Chen Gang
0 siblings, 0 replies; 80+ messages in thread
From: Chen Gang @ 2015-08-30 0:01 UTC (permalink / raw)
To: Peter Maydell, rth; +Cc: walt, Chris Metcalf, qemu-devel
On 8/29/15 22:50, Peter Maydell wrote:
> On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
>
>> + qemu_log_mask(CPU_LOG_TB_IN_ASM, " %" PRIx64 ": { ", dc->pc);
>> + if (get_Mode(bundle)) {
>> + notice_excp(dc, bundle, "y0", decode_y0(dc, bundle));
>> + qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
>> + notice_excp(dc, bundle, "y1", decode_y1(dc, bundle));
>> + qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
>> + notice_excp(dc, bundle, "y2", decode_y2(dc, bundle));
>> + } else {
>> + notice_excp(dc, bundle, "x0", decode_x0(dc, bundle));
>> + qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
>> + notice_excp(dc, bundle, "x1", decode_x1(dc, bundle));
>> + }
>
> I notice that even if the first insn in a bundle generates an
> exception we'll go ahead and generate unreachable code for
> the rest.
>
> I haven't tried to find and compare against any instruction
> set documentation, but structurally it looks good, so
>
For me, I am not quite sure it is really safe, more explanations are
welcomed.
And for each bundle, I still suggest to:
- buffering dest regs in temp regs for each pipe.
- buffering 1st exception information in env for the related pipe.
- flush temp regs to dest regs.
- gen exception based on the env information.
I assumed all exceptions which can still let working flow continue are
all in pipe x1 (at present, it should be corret), so it is enough for us
to only process 1st exception of bundle.
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions
[not found] ` <55E2822E.4000805@hotmail.com>
@ 2015-08-30 4:09 ` Chen Gang
2015-09-10 15:29 ` Chen Gang
0 siblings, 1 reply; 80+ messages in thread
From: Chen Gang @ 2015-08-30 4:09 UTC (permalink / raw)
To: rth, qemu-devel; +Cc: walt, Chris Metcalf, Peter Maydell
After download and merge the all related patches to my local qemu, for
me:
- The refactor code is really very good to me! :-)
- It cause "hello world" test program "segment fault".
Do we need fix all related issues before merge the code?
- If I need fix them after finish merging the refactor code into qemu
master, please let me know, I shall try, next.
- If it is necessary to provide related test programs, please let me
know, I shall provide them to.
Thanks.
On 8/29/15 21:19, Chen Gang wrote:
>
> Is tilegx patches OK to qemu mater tree?
>
> Or shall I do anything for it? If I should do something for it, please
> let me know, I shall try.
>
> I almost finished analyzing one gcc bug (found root cause, got correct
> result with my patch), it was waiting review. If I needn't do anything
> for tilegx merging, I shall continue to analyze tilegx gcc testsuite.
>
> Thanks.
>
> On 8/25/15 06:12, Chen Gang wrote:
>>
>> On 8/25/15 00:17, Richard Henderson wrote:
>>> I've flushed out the v13 I posted last Thursday to handle all the
>>> instructions required to execute Hello World. In the process I
>>> found a number of bugs and design flaws in v13, and reshaped the
>>> translation a bit to better handle insns with no register outputs.
>>>
>>
>> OK, thank you for your work (originally, I really did not kown that it
>> would generate so many patches -- almost 3 times that I supposed).
>>
>>
>>> Please review.
>>>
>>> After this, I would hope that Chen Gang will follow up to implement
>>> the rest of the instructions that he has identified running the
>>> gcc testsuite, and then start in on the floating point.
>>>
>>
>> OK, thanks, I shall continue based on it, after it is integrated into
>> qemu master (after Reviewed-by another members).
>>
>> During the next 2-4 days I shall try to fix one gcc bugzilla issue, then
>> turn back to qemu, hope I can succeed. (during these passed days, I sent
>> 3 paches to kernel, and 2 of them are applied, one is waiting review).
>>
>>
>> Thanks.
>>
>>>
>>> r~
>>>
>>>
>>> Chen Gang (9):
>>> linux-user: tilegx: Firstly add architecture related features
>>> linux-user: Support tilegx architecture in linux-user
>>> linux-user: Conditionalize syscalls which are not defined in tilegx
>>> target-tilegx: Add opcode basic implementation from Tilera Corporation
>>> target-tilegx: Modify opcode_tilegx.h to fit QEMU usage
>>> target-tilegx: Add special register information from Tilera
>>> Corporation
>>> target-tilegx: Add cpu basic features for linux-user
>>> target-tilegx: Add several helpers for instructions translation
>>> target-tilegx: Add TILE-Gx building files
>>>
>>> Richard Henderson (24):
>>> target-tilegx: Modify _SPECIAL_ opcodes
>>> target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1
>>> target-tilegx: Framework for decoding bundles
>>> target-tilegx: Generate SEGV properly
>>> target-tilegx: Handle simple logical operations
>>> target-tilegx: Handle arithmetic instructions
>>> target-tilegx: Handle most bit manipulation instructions
>>> target-tilegx: Handle basic load and store instructions
>>> target-tilegx: Handle post-increment load and store instructions
>>> target-tilegx: Handle unconditional jump instructions
>>> target-tilegx: Handle conditional branch instructions
>>> target-tilegx: Handle comparison instructions
>>> target-tilegx: Implement system and memory management instructions
>>> target-tilegx: Handle bitfield instructions
>>> target-tilegx: Handle shift instructions
>>> target-tilegx: Handle conditional move instructions
>>> target-tilegx: Handle scalar multiply instructions
>>> target-tilegx: Handle mask instructions
>>> target-tilegx: Handle v1cmpeq, v1cmpne
>>> target-tilegx: Handle mtspr, mfspr
>>> target-tilegx: Handle atomic instructions
>>> target-tilegx: Handle v4int_l/h
>>> target-tilegx: Handle v1shli, v1shrui
>>> target-tilegx: Handle v1shl, v1shru, v1shrs
>>>
>>> configure | 2 +
>>> default-configs/tilegx-linux-user.mak | 1 +
>>> include/elf.h | 2 +
>>> linux-user/elfload.c | 23 +
>>> linux-user/main.c | 298 +++++
>>> linux-user/syscall.c | 50 +-
>>> linux-user/syscall_defs.h | 14 +-
>>> linux-user/tilegx/syscall.h | 40 +
>>> linux-user/tilegx/syscall_nr.h | 324 +++++
>>> linux-user/tilegx/target_cpu.h | 35 +
>>> linux-user/tilegx/target_signal.h | 28 +
>>> linux-user/tilegx/target_structs.h | 46 +
>>> linux-user/tilegx/termbits.h | 274 +++++
>>> target-tilegx/Makefile.objs | 1 +
>>> target-tilegx/cpu.c | 173 +++
>>> target-tilegx/cpu.h | 177 +++
>>> target-tilegx/helper.c | 93 ++
>>> target-tilegx/helper.h | 10 +
>>> target-tilegx/opcode_tilegx.h | 1406 ++++++++++++++++++++++
>>> target-tilegx/simd_helper.c | 63 +
>>> target-tilegx/spr_def_64.h | 216 ++++
>>> target-tilegx/translate.c | 2135 +++++++++++++++++++++++++++++++++
>>> 22 files changed, 5405 insertions(+), 6 deletions(-)
>>> create mode 100644 default-configs/tilegx-linux-user.mak
>>> create mode 100644 linux-user/tilegx/syscall.h
>>> create mode 100644 linux-user/tilegx/syscall_nr.h
>>> create mode 100644 linux-user/tilegx/target_cpu.h
>>> create mode 100644 linux-user/tilegx/target_signal.h
>>> create mode 100644 linux-user/tilegx/target_structs.h
>>> create mode 100644 linux-user/tilegx/termbits.h
>>> create mode 100644 target-tilegx/Makefile.objs
>>> create mode 100644 target-tilegx/cpu.c
>>> create mode 100644 target-tilegx/cpu.h
>>> create mode 100644 target-tilegx/helper.c
>>> create mode 100644 target-tilegx/helper.h
>>> create mode 100644 target-tilegx/opcode_tilegx.h
>>> create mode 100644 target-tilegx/simd_helper.c
>>> create mode 100644 target-tilegx/spr_def_64.h
>>> create mode 100644 target-tilegx/translate.c
>>>
>>
>> --
>> Chen Gang
>>
>> Open, share, and attitude like air, water, and life which God blessed
>>
>>
>
> --
> Chen Gang
>
> Open, share, and attitude like air, water, and life which God blessed
>
>
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 23/33] target-tilegx: Handle bitfield instructions
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 23/33] target-tilegx: Handle bitfield instructions Richard Henderson
@ 2015-08-30 13:31 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-08-30 13:31 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 74 insertions(+)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 24/33] target-tilegx: Handle shift instructions
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 24/33] target-tilegx: Handle shift instructions Richard Henderson
@ 2015-08-30 13:38 ` Peter Maydell
2015-09-01 5:37 ` Richard Henderson
0 siblings, 1 reply; 80+ messages in thread
From: Peter Maydell @ 2015-08-30 13:38 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 57 +++++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 55 insertions(+), 2 deletions(-)
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index 6be751b..4e6d577 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -474,6 +474,7 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
> TCGv tdest = dest_gr(dc, dest);
> TCGv tsrca = load_gr(dc, srca);
> TCGv tsrcb = load_gr(dc, srcb);
> + TCGv t0;
Personally I would restrict the scope of this to just the
case block where it's used.
> case OE_RRR(SHRUX, 0, X0):
> case OE_RRR(SHRUX, 0, X1):
> + t0 = tcg_temp_new();
> + tcg_gen_andi_tl(t0, tsrcb, 31);
> + tcg_gen_ext32u_tl(tdest, tsrca);
> + tcg_gen_shl_tl(tdest, tdest, t0);
> + tcg_gen_ext32s_tl(tdest, tdest);
> + tcg_temp_free(t0);
> + mnemonic = "shrux";
> + break;
Using shl for a shift right doesn't look right...
> case OE_SH(SHRUI, X0):
> case OE_SH(SHRUI, X1):
> case OE_SH(SHRUI, Y0):
> case OE_SH(SHRUI, Y1):
> + tcg_gen_shri_tl(tdest, tsrca, imm);
> + mnemonic = "shrui";
> + break;
> case OE_SH(SHRUXI, X0):
> case OE_SH(SHRUXI, X1):
> + if ((imm & 31) == 0) {
> + tcg_gen_ext32s_tl(tdest, tsrca);
> + } else {
> + tcg_gen_ext32u_tl(tdest, tsrca);
> + tcg_gen_shli_tl(tdest, tdest, imm & 31);
Shift left used when shift right intended ?
> + }
> + mnemonic = "shlxi";
> + break;
> case OE_SH(V1SHLI, X0):
> case OE_SH(V1SHLI, X1):
> case OE_SH(V1SHRSI, X0):
> @@ -1096,6 +1148,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
> case OE_SH(V2SHRSI, X1):
> case OE_SH(V2SHRUI, X0):
> case OE_SH(V2SHRUI, X1):
> + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
Why does this change appear in this patch?
>
> case OE(ADDLI_OPCODE_X0, 0, X0):
> case OE(ADDLI_OPCODE_X1, 0, X1):
> --
> 2.4.3
>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 25/33] target-tilegx: Handle conditional move instructions
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 25/33] target-tilegx: Handle conditional move instructions Richard Henderson
@ 2015-08-30 13:40 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-08-30 13:40 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 26/33] target-tilegx: Handle scalar multiply instructions
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 26/33] target-tilegx: Handle scalar multiply instructions Richard Henderson
@ 2015-08-30 13:46 ` Peter Maydell
2015-09-01 5:42 ` Richard Henderson
0 siblings, 1 reply; 80+ messages in thread
From: Peter Maydell @ 2015-08-30 13:46 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 112 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 112 insertions(+)
It seems a shame that these are all 32x32->64 multiplies
(or in some cases 32x32->32), but we won't actually be able
to make use of a host CPU 32x32->64 instruction.
Still, these give the right results I think so
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 27/33] target-tilegx: Handle mask instructions
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 27/33] target-tilegx: Handle mask instructions Richard Henderson
@ 2015-08-30 13:52 ` Peter Maydell
2015-09-01 5:43 ` Richard Henderson
0 siblings, 1 reply; 80+ messages in thread
From: Peter Maydell @ 2015-08-30 13:52 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index 51ee158..af4b34a 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -647,11 +647,15 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
> case OE_RRR(FSINGLE_MUL2, 0, X0):
> case OE_RRR(FSINGLE_PACK2, 0, X0):
> case OE_RRR(FSINGLE_SUB1, 0, X0):
> + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> case OE_RRR(MNZ, 0, X0):
> case OE_RRR(MNZ, 0, X1):
> case OE_RRR(MNZ, 4, Y0):
> case OE_RRR(MNZ, 4, Y1):
> - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> + t0 = load_zero(dc);
> + tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, t0, tsrcb, t0);
> + mnemonic = "mnz";
> + break;
> case OE_RRR(MULAX, 0, X0):
> case OE_RRR(MULAX, 3, Y0):
> tcg_gen_mul_tl(tdest, tsrca, tsrcb);
> @@ -767,7 +771,10 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
> case OE_RRR(MZ, 0, X1):
> case OE_RRR(MZ, 4, Y0):
> case OE_RRR(MZ, 4, Y1):
> - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> + t0 = load_zero(dc);
> + tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, t0, tsrcb, t0);
> + mnemonic = "mz";
> + break;
> case OE_RRR(NOR, 0, X0):
> case OE_RRR(NOR, 0, X1):
> case OE_RRR(NOR, 5, Y0):
> --
> 2.4.3
>
I *think* this code is correct, but the ISA manual perplexes me
entirely. Why on earth would you describe anything as "compute
the boolean AND of something with a value of all ones", when that's
just a no-op? I can't see what I'm missing that means they
didn't just describe 'mz' as "dest = srcA ? srcB : 0".
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 28/33] target-tilegx: Handle v1cmpeq, v1cmpne
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 28/33] target-tilegx: Handle v1cmpeq, v1cmpne Richard Henderson
@ 2015-08-30 15:11 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-08-30 15:11 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index af4b34a..1224a8e 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -93,6 +93,8 @@ typedef struct {
> #define OE_IM(E,XY) OE(IMM8_OPCODE_##XY, E##_IMM8_OPCODE_##XY, XY)
> #define OE_SH(E,XY) OE(SHIFT_OPCODE_##XY, E##_SHIFT_OPCODE_##XY, XY)
>
> +#define V1_IMM(X) (((X) & 0xff) * 0x0101010101010101ull)
> +
>
> static void gen_exception(DisasContext *dc, TileExcp num)
> {
> @@ -238,6 +240,41 @@ static void gen_mul_half(TCGv tdest, TCGv tsrca, TCGv tsrcb, int ha, int hb)
> tcg_temp_free(t);
> }
>
> +/* Equality comparison with zero can be done quickly and efficiently. */
> +static void gen_v1cmpeq0(TCGv v)
> +{
> + TCGv m = tcg_const_tl(V1_IMM(0x7f));
> + TCGv c = tcg_temp_new();
> +
> + /* ~(((a & m) + m) | m | a). Sets the msb for each byte == 0. */
> + tcg_gen_and_tl(c, v, m);
> + tcg_gen_add_tl(c, c, m);
> + tcg_gen_or_tl(c, c, m);
> + tcg_gen_nor_tl(c, c, v);
> + tcg_temp_free(m);
It would be nice to be consistent with whether we're using 'v'
or 'a' for the input value in the code and the comment.
otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 29/33] target-tilegx: Handle mtspr, mfspr
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 29/33] target-tilegx: Handle mtspr, mfspr Richard Henderson
@ 2015-08-30 15:18 ` Peter Maydell
2015-09-01 5:48 ` Richard Henderson
0 siblings, 1 reply; 80+ messages in thread
From: Peter Maydell @ 2015-08-30 15:18 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 76 +++++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 73 insertions(+), 3 deletions(-)
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index 1224a8e..210e912 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -24,6 +24,7 @@
> #include "tcg-op.h"
> #include "exec/cpu_ldst.h"
> #include "opcode_tilegx.h"
> +#include "spr_def_64.h"
>
> #define FMT64X "%016" PRIx64
>
> @@ -1226,9 +1227,6 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
> tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
> mnemonic = "ldna_add";
> break;
> - case OE_IM(MFSPR, X1):
> - case OE_IM(MTSPR, X1):
> - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> case OE_IM(ORI, X0):
> case OE_IM(ORI, X1):
> tcg_gen_ori_tl(tdest, tsrca, imm);
> @@ -1528,6 +1526,74 @@ static TileExcp gen_jump_opcode_x1(DisasContext *dc, unsigned ext, int off)
> return TILEGX_EXCP_NONE;
> }
>
> +typedef struct {
> + const char *name;
> + intptr_t offset;
> + void (*get)(TCGv, TCGv_ptr);
> + void (*put)(TCGv_ptr, TCGv);
> +} TileSPR;
> +
> +static const TileSPR *find_spr(unsigned spr)
> +{
> + /* Allow the compiler to construct the binary search tree. */
This feels a bit overly clever to me but if we only have
three registers anyway it doesn't matter much.
> +#define D(N, O, G, P) \
> + case SPR_##N: { static const TileSPR x = { #N, O, G, P }; return &x; }
> +
> + switch (spr) {
> + D(CMPEXCH_VALUE,
> + offsetof(CPUTLGState, spregs[TILEGX_SPR_CMPEXCH]), 0, 0)
> + D(SIM_CONTROL,
> + offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0)
> + D(INTERRUPT_CRITICAL_SECTION,
> + offsetof(CPUTLGState, spregs[TILEGX_SPR_SIM_CONTROL]), 0, 0)
Aren't the offsets on these two backwards ?
> + }
> +
> +#undef D
> +
> + qemu_log_mask(LOG_UNIMP, "UNIMP SPR %u\n", spr);
> + return NULL;
> +}
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 31/33] target-tilegx: Handle v4int_l/h
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 31/33] target-tilegx: Handle v4int_l/h Richard Henderson
@ 2015-08-30 15:20 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-08-30 15:20 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
> index 2a0798a..e922aee 100644
> --- a/target-tilegx/translate.c
> +++ b/target-tilegx/translate.c
> @@ -1125,10 +1125,18 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
> case OE_RRR(V4ADDSC, 0, X1):
> case OE_RRR(V4ADD, 0, X0):
> case OE_RRR(V4ADD, 0, X1):
> + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
> case OE_RRR(V4INT_H, 0, X0):
> case OE_RRR(V4INT_H, 0, X1):
> + tcg_gen_shri_tl(tdest, tsrcb, 32);
> + tcg_gen_deposit_tl(tdest, tsrca, tdest, 0, 32);
> + mnemonic = "v4int_h";
> + break;
> case OE_RRR(V4INT_L, 0, X0):
> case OE_RRR(V4INT_L, 0, X1):
> + tcg_gen_deposit_tl(tdest, tsrcb, tsrca, 32, 32);
> + mnemonic = "v4int_l";
> + break;
> case OE_RRR(V4PACKSC, 0, X0):
> case OE_RRR(V4PACKSC, 0, X1):
> case OE_RRR(V4SHLSC, 0, X0):
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 32/33] target-tilegx: Handle v1shli, v1shrui
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 32/33] target-tilegx: Handle v1shli, v1shrui Richard Henderson
@ 2015-08-30 15:23 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-08-30 15:23 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/translate.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 33/33] target-tilegx: Handle v1shl, v1shru, v1shrs
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 33/33] target-tilegx: Handle v1shl, v1shru, v1shrs Richard Henderson
@ 2015-08-30 15:28 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-08-30 15:28 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-tilegx/Makefile.objs | 2 +-
> target-tilegx/helper.h | 4 +++
> target-tilegx/simd_helper.c | 63 +++++++++++++++++++++++++++++++++++++++++++++
> target-tilegx/translate.c | 17 +++++++++++-
> 4 files changed, 84 insertions(+), 2 deletions(-)
> create mode 100644 target-tilegx/simd_helper.c
>
> diff --git a/target-tilegx/Makefile.objs b/target-tilegx/Makefile.objs
> index 8b3dc76..0db778f 100644
> --- a/target-tilegx/Makefile.objs
> +++ b/target-tilegx/Makefile.objs
> @@ -1 +1 @@
> -obj-y += cpu.o translate.o helper.o
> +obj-y += cpu.o translate.o helper.o simd_helper.o
> diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
> index 644d313..766f5f2 100644
> --- a/target-tilegx/helper.h
> +++ b/target-tilegx/helper.h
> @@ -4,3 +4,7 @@ DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
> DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64)
> DEF_HELPER_FLAGS_1(revbits, TCG_CALL_NO_RWG_SE, i64, i64)
> DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
> +
> +DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> +DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> +DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)
> diff --git a/target-tilegx/simd_helper.c b/target-tilegx/simd_helper.c
> new file mode 100644
> index 0000000..7670d4a
> --- /dev/null
> +++ b/target-tilegx/simd_helper.c
> @@ -0,0 +1,63 @@
> +/*
> + * QEMU TILE-Gx helpers
> + *
> + * Copyright (c) 2015 Chen Gang
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2.1 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see
> + * <http://www.gnu.org/licenses/lgpl-2.1.html>
> + */
> +
> +#include "cpu.h"
> +#include "qemu-common.h"
> +#include "exec/helper-proto.h"
> +
> +
> +uint64_t helper_v1shl(uint64_t a, uint64_t b)
> +{
> + uint64_t r = 0;
> + int i;
> +
> + for (i = 0; i < 64; i += 8) {
> + uint64_t m = 0xffULL << i;
> + uint64_t be = (b >> i) & 7;
> + r |= ((a & m) << be) & m;
> + }
This seems to be shifting each byte in the input vector
by an amount encoded in each byte in b, but the ISA says
this instruction shifts each byte by the same amount.
Similarly for v1shru and v1shrs.
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 11/33] target-tilegx: Framework for decoding bundles
2015-08-29 21:08 ` Peter Maydell
@ 2015-09-01 1:58 ` Richard Henderson
0 siblings, 0 replies; 80+ messages in thread
From: Richard Henderson @ 2015-09-01 1:58 UTC (permalink / raw)
To: Peter Maydell; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 08/29/2015 02:08 PM, Peter Maydell wrote:
> On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
>> Signed-off-by: Richard Henderson <rth@twiddle.net>
>> + if (dc->jmp.cond != TCG_COND_NEVER) {
>> + if (dc->jmp.cond == TCG_COND_ALWAYS) {
>> + tcg_gen_mov_i64(cpu_pc, dc->jmp.dest);
>> + } else {
>> + TCGv next = tcg_const_i64(dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
>> + tcg_gen_movcond_i64(dc->jmp.cond, cpu_pc,
>> + dc->jmp.val1, load_zero(dc),
>> + dc->jmp.dest, next);
>> + tcg_temp_free_i64(dc->jmp.val1);
>> + tcg_temp_free_i64(next);
>> + }
>> + tcg_temp_free_i64(dc->jmp.dest);
>> + tcg_gen_exit_tb(0);
>> + dc->exit_tb = true;
>> + }
>
> Doing conditional branches with movcond to pc means we'll
> never be able to link TBs which end with conditional branches,
> right?
The structure of the code is such that we could use goto_tb.
I just didn't want to complicate the initial implementation.
r~
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 14/33] target-tilegx: Handle simple logical operations
2015-08-29 14:58 ` Peter Maydell
@ 2015-09-01 2:10 ` Richard Henderson
0 siblings, 0 replies; 80+ messages in thread
From: Richard Henderson @ 2015-09-01 2:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 08/29/2015 07:58 AM, Peter Maydell wrote:
> On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
>> Signed-off-by: Richard Henderson <rth@twiddle.net>
>> ---
>> target-tilegx/translate.c | 99 +++++++++++++++++++++++++++++++++++++++++++++--
>> 1 file changed, 96 insertions(+), 3 deletions(-)
>>
>> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
>> index a2d597d..066d351 100644
>> --- a/target-tilegx/translate.c
>> +++ b/target-tilegx/translate.c
>> @@ -106,9 +106,64 @@ static void gen_exception(DisasContext *dc, TileExcp num)
>> dc->exit_tb = true;
>> }
>>
>> +static bool check_gr(DisasContext *dc, uint8_t reg)
>> +{
>> + if (likely(reg < TILEGX_R_COUNT)) {
>> + return true;
>> + }
>> +
>> + switch (reg) {
>> + case TILEGX_R_SN:
>> + case TILEGX_R_ZERO:
>> + break;
>> + case TILEGX_R_IDN0:
>> + case TILEGX_R_IDN1:
>> + gen_exception(dc, TILEGX_EXCP_REG_IDN_ACCESS);
>> + break;
>> + case TILEGX_R_UDN0:
>> + case TILEGX_R_UDN1:
>> + case TILEGX_R_UDN2:
>> + case TILEGX_R_UDN3:
>> + gen_exception(dc, TILEGX_EXCP_REG_UDN_ACCESS);
>
> Why does this function generate an exception immediately
> rather than returning a TILEGX_EXCP_* code the way the
> decode framework seems to be set up to work?
So that we can simply return a TCGv from the load_gr and dest_gr functions, and
their users don't have to check for an error code.
r~
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 16/33] target-tilegx: Handle most bit manipulation instructions
2015-08-29 15:26 ` Peter Maydell
@ 2015-09-01 2:26 ` Richard Henderson
0 siblings, 0 replies; 80+ messages in thread
From: Richard Henderson @ 2015-09-01 2:26 UTC (permalink / raw)
To: Peter Maydell; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 08/29/2015 08:26 AM, Peter Maydell wrote:
> Incidentally I deduce that we're not planning to support bigendian
> mode?
*shrug* I hadn't thought about it. Little-endian seems to be the default for
the toolchain. The pre-built userland available for download only contains
little-endian code.
r~
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 22/33] target-tilegx: Implement system and memory management instructions
2015-08-29 21:21 ` Peter Maydell
@ 2015-09-01 5:16 ` Richard Henderson
2015-09-01 8:23 ` Peter Maydell
0 siblings, 1 reply; 80+ messages in thread
From: Richard Henderson @ 2015-09-01 5:16 UTC (permalink / raw)
To: Peter Maydell; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 08/29/2015 02:21 PM, Peter Maydell wrote:
>> + case OE_RR_X1(SWINT3):
>> + ret = TILEGX_EXCP_OPCODE_UNKNOWN;
>> + mnemonic = "swint3";
>> + goto done0;
>> + done0:
>
> goto to immediately following label ?
Sometimes nicer than fallthrough when future patches might interpose extra code.
>> @@ -284,8 +339,12 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
>> dc->jmp.cond = TCG_COND_ALWAYS;
>> dc->jmp.dest = tcg_temp_new();
>> tcg_gen_andi_tl(dc->jmp.dest, load_gr(dc, srca), ~7);
>
> Should this really fall through into the added check ?
>
>> + done1:
>> + if (dest && ret == TILEGX_EXCP_NONE) {
>> + ret = TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
>> + }
...
>> case OE_RR_X1(LNK):
>> case OE_RR_Y1(LNK):
>> if (srca) {
>> - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
>> + ret = TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
>
> This code change seems unrelated to the rest of the patch?
> Also we'll end up printing the disassembly as "lnk" rather
> than whatever we should print for undefined instructions.
I'm not really sure what to do with reserved operand fields on this
architecture. Raising an exception is what Chen started with, but the encoding
for brk suggests that they're ignored.
Suggestions?
r~
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 24/33] target-tilegx: Handle shift instructions
2015-08-30 13:38 ` Peter Maydell
@ 2015-09-01 5:37 ` Richard Henderson
0 siblings, 0 replies; 80+ messages in thread
From: Richard Henderson @ 2015-09-01 5:37 UTC (permalink / raw)
To: Peter Maydell; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 08/30/2015 06:38 AM, Peter Maydell wrote:
> On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
>> Signed-off-by: Richard Henderson <rth@twiddle.net>
>> ---
>> target-tilegx/translate.c | 57 +++++++++++++++++++++++++++++++++++++++++++++--
>> 1 file changed, 55 insertions(+), 2 deletions(-)
>>
>> diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
>> index 6be751b..4e6d577 100644
>> --- a/target-tilegx/translate.c
>> +++ b/target-tilegx/translate.c
>> @@ -474,6 +474,7 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
>> TCGv tdest = dest_gr(dc, dest);
>> TCGv tsrca = load_gr(dc, srca);
>> TCGv tsrcb = load_gr(dc, srcb);
>> + TCGv t0;
>
> Personally I would restrict the scope of this to just the
> case block where it's used.
It'll get used lots more by other insns in subsequent patches. While
restricting the scope is arguably ideal, it adds 3 lines for each use and
brevity has its own appeal.
> Using shl for a shift right doesn't look right...
...
> Shift left used when shift right intended ?
Fixed.
>> @@ -1096,6 +1148,7 @@ static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
>> case OE_SH(V2SHRSI, X1):
>> case OE_SH(V2SHRUI, X0):
>> case OE_SH(V2SHRUI, X1):
>> + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
>
> Why does this change appear in this patch?
I'm sure I meant to rebase it into the patch implementing ADDLI.
>
>>
>> case OE(ADDLI_OPCODE_X0, 0, X0):
>> case OE(ADDLI_OPCODE_X1, 0, X1):
r~
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 26/33] target-tilegx: Handle scalar multiply instructions
2015-08-30 13:46 ` Peter Maydell
@ 2015-09-01 5:42 ` Richard Henderson
0 siblings, 0 replies; 80+ messages in thread
From: Richard Henderson @ 2015-09-01 5:42 UTC (permalink / raw)
To: Peter Maydell; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 08/30/2015 06:46 AM, Peter Maydell wrote:
> On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote:
>> Signed-off-by: Richard Henderson <rth@twiddle.net>
>> ---
>> target-tilegx/translate.c | 112 ++++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 112 insertions(+)
>
> It seems a shame that these are all 32x32->64 multiplies
> (or in some cases 32x32->32), but we won't actually be able
> to make use of a host CPU 32x32->64 instruction.
Indeed. For the most part I've been assuming a 64-bit host for all the ports
I've been working on recently. At which point it's not really worth doing all
of the truncation and extension required to use such insns.
r~
>
> Still, these give the right results I think so
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 27/33] target-tilegx: Handle mask instructions
2015-08-30 13:52 ` Peter Maydell
@ 2015-09-01 5:43 ` Richard Henderson
0 siblings, 0 replies; 80+ messages in thread
From: Richard Henderson @ 2015-09-01 5:43 UTC (permalink / raw)
To: Peter Maydell; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 08/30/2015 06:52 AM, Peter Maydell wrote:
> I *think* this code is correct, but the ISA manual perplexes me
> entirely. Why on earth would you describe anything as "compute
> the boolean AND of something with a value of all ones", when that's
> just a no-op? I can't see what I'm missing that means they
> didn't just describe 'mz' as "dest = srcA ? srcB : 0".
Clearly someone who decided that was the best way to implement a conditional
move in hardware. The language just propagated back to the manual.
r~
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 29/33] target-tilegx: Handle mtspr, mfspr
2015-08-30 15:18 ` Peter Maydell
@ 2015-09-01 5:48 ` Richard Henderson
0 siblings, 0 replies; 80+ messages in thread
From: Richard Henderson @ 2015-09-01 5:48 UTC (permalink / raw)
To: Peter Maydell; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 08/30/2015 08:18 AM, Peter Maydell wrote:
>> +static const TileSPR *find_spr(unsigned spr)
>> +{
>> + /* Allow the compiler to construct the binary search tree. */
>
> This feels a bit overly clever to me but if we only have
> three registers anyway it doesn't matter much.
I was just forward looking to system mode. There's a *lot* of sprs defined in
spr_def_64.h.
>> + D(SIM_CONTROL,
>> + offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0)
>> + D(INTERRUPT_CRITICAL_SECTION,
>> + offsetof(CPUTLGState, spregs[TILEGX_SPR_SIM_CONTROL]), 0, 0)
>
> Aren't the offsets on these two backwards ?
Fixed, thanks.
r~
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 22/33] target-tilegx: Implement system and memory management instructions
2015-09-01 5:16 ` Richard Henderson
@ 2015-09-01 8:23 ` Peter Maydell
0 siblings, 0 replies; 80+ messages in thread
From: Peter Maydell @ 2015-09-01 8:23 UTC (permalink / raw)
To: Richard Henderson; +Cc: walt, Chris Metcalf, QEMU Developers, Chen Gang
On 1 September 2015 at 06:16, Richard Henderson <rth@twiddle.net> wrote:
> I'm not really sure what to do with reserved operand fields on this
> architecture. Raising an exception is what Chen started with, but the
> encoding for brk suggests that they're ignored.
The ISA says "Implementations are permitted, but not required, to take
an Illegal Instruction interrupt when detecting a nonzero value in an
unused instruction field.".
Raising an exception seems like the best option to me.
The description of 'bpt' suggests that it's just "a particular
pattern we guarantee will always generate an illegal instruction
interrupt", and then the kernel figures out that it was a bpt
in particular by looking at the instruction:
http://lxr.free-electrons.com/source/arch/tile/kernel/traps.c#L212
Similarly for 'raise', handled a little further up in that file.
In QEMU, we probably want to deal with this by having the insns
generate an illegal instruction exception in translate.c and
then examine the instruction at PC in the linux-user/main.c
loop to see if it should be special-cased as 'bpt', etc.
thanks
-- PMM
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions
2015-08-30 4:09 ` Chen Gang
@ 2015-09-10 15:29 ` Chen Gang
0 siblings, 0 replies; 80+ messages in thread
From: Chen Gang @ 2015-09-10 15:29 UTC (permalink / raw)
To: rth, qemu-devel; +Cc: walt, Chris Metcalf, Peter Maydell
Hello all:
It looks tilegx still outside of qemu master tree.
I guess, I have to still use my own implementation to continue analyzing
gcc testsuite (or I am not quite sure whether I can finish analyzing
within this month).
Welcome any ideas, suggestions and completions.
Thanks.
On 8/30/15 12:09, Chen Gang wrote:
>
> After download and merge the all related patches to my local qemu, for
> me:
>
> - The refactor code is really very good to me! :-)
>
> - It cause "hello world" test program "segment fault".
>
> Do we need fix all related issues before merge the code?
>
> - If I need fix them after finish merging the refactor code into qemu
> master, please let me know, I shall try, next.
>
> - If it is necessary to provide related test programs, please let me
> know, I shall provide them to.
>
> Thanks.
>
> On 8/29/15 21:19, Chen Gang wrote:
>>
>> Is tilegx patches OK to qemu mater tree?
>>
>> Or shall I do anything for it? If I should do something for it, please
>> let me know, I shall try.
>>
>> I almost finished analyzing one gcc bug (found root cause, got correct
>> result with my patch), it was waiting review. If I needn't do anything
>> for tilegx merging, I shall continue to analyze tilegx gcc testsuite.
>>
>> Thanks.
>>
>> On 8/25/15 06:12, Chen Gang wrote:
>>>
>>> On 8/25/15 00:17, Richard Henderson wrote:
>>>> I've flushed out the v13 I posted last Thursday to handle all the
>>>> instructions required to execute Hello World. In the process I
>>>> found a number of bugs and design flaws in v13, and reshaped the
>>>> translation a bit to better handle insns with no register outputs.
>>>>
>>>
>>> OK, thank you for your work (originally, I really did not kown that it
>>> would generate so many patches -- almost 3 times that I supposed).
>>>
>>>
>>>> Please review.
>>>>
>>>> After this, I would hope that Chen Gang will follow up to implement
>>>> the rest of the instructions that he has identified running the
>>>> gcc testsuite, and then start in on the floating point.
>>>>
>>>
>>> OK, thanks, I shall continue based on it, after it is integrated into
>>> qemu master (after Reviewed-by another members).
>>>
>>> During the next 2-4 days I shall try to fix one gcc bugzilla issue, then
>>> turn back to qemu, hope I can succeed. (during these passed days, I sent
>>> 3 paches to kernel, and 2 of them are applied, one is waiting review).
>>>
>>>
>>> Thanks.
>>>
>>>>
>>>> r~
>>>>
>>>>
>>>> Chen Gang (9):
>>>> linux-user: tilegx: Firstly add architecture related features
>>>> linux-user: Support tilegx architecture in linux-user
>>>> linux-user: Conditionalize syscalls which are not defined in tilegx
>>>> target-tilegx: Add opcode basic implementation from Tilera Corporation
>>>> target-tilegx: Modify opcode_tilegx.h to fit QEMU usage
>>>> target-tilegx: Add special register information from Tilera
>>>> Corporation
>>>> target-tilegx: Add cpu basic features for linux-user
>>>> target-tilegx: Add several helpers for instructions translation
>>>> target-tilegx: Add TILE-Gx building files
>>>>
>>>> Richard Henderson (24):
>>>> target-tilegx: Modify _SPECIAL_ opcodes
>>>> target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1
>>>> target-tilegx: Framework for decoding bundles
>>>> target-tilegx: Generate SEGV properly
>>>> target-tilegx: Handle simple logical operations
>>>> target-tilegx: Handle arithmetic instructions
>>>> target-tilegx: Handle most bit manipulation instructions
>>>> target-tilegx: Handle basic load and store instructions
>>>> target-tilegx: Handle post-increment load and store instructions
>>>> target-tilegx: Handle unconditional jump instructions
>>>> target-tilegx: Handle conditional branch instructions
>>>> target-tilegx: Handle comparison instructions
>>>> target-tilegx: Implement system and memory management instructions
>>>> target-tilegx: Handle bitfield instructions
>>>> target-tilegx: Handle shift instructions
>>>> target-tilegx: Handle conditional move instructions
>>>> target-tilegx: Handle scalar multiply instructions
>>>> target-tilegx: Handle mask instructions
>>>> target-tilegx: Handle v1cmpeq, v1cmpne
>>>> target-tilegx: Handle mtspr, mfspr
>>>> target-tilegx: Handle atomic instructions
>>>> target-tilegx: Handle v4int_l/h
>>>> target-tilegx: Handle v1shli, v1shrui
>>>> target-tilegx: Handle v1shl, v1shru, v1shrs
>>>>
>>>> configure | 2 +
>>>> default-configs/tilegx-linux-user.mak | 1 +
>>>> include/elf.h | 2 +
>>>> linux-user/elfload.c | 23 +
>>>> linux-user/main.c | 298 +++++
>>>> linux-user/syscall.c | 50 +-
>>>> linux-user/syscall_defs.h | 14 +-
>>>> linux-user/tilegx/syscall.h | 40 +
>>>> linux-user/tilegx/syscall_nr.h | 324 +++++
>>>> linux-user/tilegx/target_cpu.h | 35 +
>>>> linux-user/tilegx/target_signal.h | 28 +
>>>> linux-user/tilegx/target_structs.h | 46 +
>>>> linux-user/tilegx/termbits.h | 274 +++++
>>>> target-tilegx/Makefile.objs | 1 +
>>>> target-tilegx/cpu.c | 173 +++
>>>> target-tilegx/cpu.h | 177 +++
>>>> target-tilegx/helper.c | 93 ++
>>>> target-tilegx/helper.h | 10 +
>>>> target-tilegx/opcode_tilegx.h | 1406 ++++++++++++++++++++++
>>>> target-tilegx/simd_helper.c | 63 +
>>>> target-tilegx/spr_def_64.h | 216 ++++
>>>> target-tilegx/translate.c | 2135 +++++++++++++++++++++++++++++++++
>>>> 22 files changed, 5405 insertions(+), 6 deletions(-)
>>>> create mode 100644 default-configs/tilegx-linux-user.mak
>>>> create mode 100644 linux-user/tilegx/syscall.h
>>>> create mode 100644 linux-user/tilegx/syscall_nr.h
>>>> create mode 100644 linux-user/tilegx/target_cpu.h
>>>> create mode 100644 linux-user/tilegx/target_signal.h
>>>> create mode 100644 linux-user/tilegx/target_structs.h
>>>> create mode 100644 linux-user/tilegx/termbits.h
>>>> create mode 100644 target-tilegx/Makefile.objs
>>>> create mode 100644 target-tilegx/cpu.c
>>>> create mode 100644 target-tilegx/cpu.h
>>>> create mode 100644 target-tilegx/helper.c
>>>> create mode 100644 target-tilegx/helper.h
>>>> create mode 100644 target-tilegx/opcode_tilegx.h
>>>> create mode 100644 target-tilegx/simd_helper.c
>>>> create mode 100644 target-tilegx/spr_def_64.h
>>>> create mode 100644 target-tilegx/translate.c
>>>>
>>>
>>> --
>>> Chen Gang
>>>
>>> Open, share, and attitude like air, water, and life which God blessed
>>>
>>>
>>
>> --
>> Chen Gang
>>
>> Open, share, and attitude like air, water, and life which God blessed
>>
>>
>
> --
> Chen Gang
>
> Open, share, and attitude like air, water, and life which God blessed
>
>
--
Chen Gang (陈刚)
Open, share, and attitude like air, water, and life which God blessed
^ permalink raw reply [flat|nested] 80+ messages in thread
end of thread, other threads:[~2015-09-10 15:27 UTC | newest]
Thread overview: 80+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-08-24 16:17 [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 01/33] linux-user: tilegx: Firstly add architecture related features Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 02/33] linux-user: Support tilegx architecture in linux-user Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 03/33] linux-user: Conditionalize syscalls which are not defined in tilegx Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 04/33] target-tilegx: Add opcode basic implementation from Tilera Corporation Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 05/33] target-tilegx: Modify opcode_tilegx.h to fit QEMU usage Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 06/33] target-tilegx: Modify _SPECIAL_ opcodes Richard Henderson
2015-08-29 14:29 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 07/33] target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 Richard Henderson
2015-08-24 16:29 ` Peter Maydell
2015-08-24 16:43 ` Richard Henderson
2015-08-26 17:11 ` Chris Metcalf
2015-08-29 14:30 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 08/33] target-tilegx: Add special register information from Tilera Corporation Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 09/33] target-tilegx: Add cpu basic features for linux-user Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 10/33] target-tilegx: Add several helpers for instructions translation Richard Henderson
2015-08-29 14:37 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 11/33] target-tilegx: Framework for decoding bundles Richard Henderson
2015-08-29 14:50 ` Peter Maydell
[not found] ` <55E24808.5000302@hotmail.com>
2015-08-30 0:01 ` Chen Gang
2015-08-29 21:08 ` Peter Maydell
2015-09-01 1:58 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 12/33] target-tilegx: Generate SEGV properly Richard Henderson
2015-08-29 14:51 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 14/33] target-tilegx: Handle simple logical operations Richard Henderson
2015-08-29 14:58 ` Peter Maydell
2015-09-01 2:10 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 15/33] target-tilegx: Handle arithmetic instructions Richard Henderson
2015-08-29 15:03 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 16/33] target-tilegx: Handle most bit manipulation instructions Richard Henderson
2015-08-29 15:26 ` Peter Maydell
2015-09-01 2:26 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 17/33] target-tilegx: Handle basic load and store instructions Richard Henderson
2015-08-29 20:45 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 18/33] target-tilegx: Handle post-increment " Richard Henderson
2015-08-29 20:52 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 19/33] target-tilegx: Handle unconditional jump instructions Richard Henderson
2015-08-29 21:00 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 20/33] target-tilegx: Handle conditional branch instructions Richard Henderson
2015-08-29 21:08 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 21/33] target-tilegx: Handle comparison instructions Richard Henderson
2015-08-29 21:12 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 22/33] target-tilegx: Implement system and memory management instructions Richard Henderson
2015-08-29 21:21 ` Peter Maydell
2015-09-01 5:16 ` Richard Henderson
2015-09-01 8:23 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 23/33] target-tilegx: Handle bitfield instructions Richard Henderson
2015-08-30 13:31 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 24/33] target-tilegx: Handle shift instructions Richard Henderson
2015-08-30 13:38 ` Peter Maydell
2015-09-01 5:37 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 25/33] target-tilegx: Handle conditional move instructions Richard Henderson
2015-08-30 13:40 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 26/33] target-tilegx: Handle scalar multiply instructions Richard Henderson
2015-08-30 13:46 ` Peter Maydell
2015-09-01 5:42 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 27/33] target-tilegx: Handle mask instructions Richard Henderson
2015-08-30 13:52 ` Peter Maydell
2015-09-01 5:43 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 28/33] target-tilegx: Handle v1cmpeq, v1cmpne Richard Henderson
2015-08-30 15:11 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 29/33] target-tilegx: Handle mtspr, mfspr Richard Henderson
2015-08-30 15:18 ` Peter Maydell
2015-09-01 5:48 ` Richard Henderson
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 30/33] target-tilegx: Handle atomic instructions Richard Henderson
2015-08-25 4:15 ` Richard Henderson
[not found] ` <55DC69B0.1040000@hotmail.com>
2015-08-25 13:11 ` Chen Gang
2015-08-25 13:12 ` Chen Gang
2015-08-25 14:28 ` Richard Henderson
[not found] ` <55DCE21F.9000103@hotmail.com>
2015-08-25 21:45 ` Chen Gang
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 31/33] target-tilegx: Handle v4int_l/h Richard Henderson
2015-08-30 15:20 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 32/33] target-tilegx: Handle v1shli, v1shrui Richard Henderson
2015-08-30 15:23 ` Peter Maydell
2015-08-24 16:17 ` [Qemu-devel] [PATCH v14 33/33] target-tilegx: Handle v1shl, v1shru, v1shrs Richard Henderson
2015-08-30 15:28 ` Peter Maydell
[not found] ` <55DB96D7.9000105@hotmail.com>
2015-08-24 22:12 ` [Qemu-devel] [PATCH v14 00/33] TileGX basic instructions Chen Gang
[not found] ` <55E1B1AF.3040407@hotmail.com>
2015-08-29 13:19 ` Chen Gang
[not found] ` <55E2822E.4000805@hotmail.com>
2015-08-30 4:09 ` Chen Gang
2015-09-10 15:29 ` Chen Gang
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.